Preamble

A Novel Pixel-Chip-Based Region-of-Interest Readout Circuit Design Shi-Qiang Zhou, Li-Rong Xie, Dong Wang, Cheng Lian, Si-Ying Liu, Zi-Yi Zhang, Xiang-Ming Hong-Bang Liu, Chao-Song Gao, Jun Liu, Huan-Bo Feng, Zhuo Zhou, Di-Fan Yi, Meng-Ping Ni Fang, Ran Chen, Yan-Jun Luo, Yi-Chen Tong, Meng-Xin Lu, and Chun-Lai Dong 1 PLAC, Key Laboratory of Quark & Lepton Physics (MOE), Central China Normal University, Wuhan 430079, China.

Guangxi Key Laboratory for Relativistic Astrophysics, School of Physical Science and Technology, Guangxi University, Nanning 530004, China.

School of Physical Science, University of Chinese Academy of Sciences, Beijing 100049, China.

This paper presents a novel pixel chip readout scheme: the Region-of-Interest Readout Circuit (ROIRC), which is designed for large area, large array pixel chips and Gas Pixel Detector (GPD). This design employs a sentinel pixel detection strategy, enabling rapid identification and prioritized readout of the pixel regions containing signal events. During the scanning readout of these signal events, ROIRC employs a Block-based readout approach, effectively minimizing the readout of non-signal pixels. The functionality of ROIRC has been successfully implemented on both the ASIC and FPGA platforms. In the tests of the ROIRC, the pixel chip embedded in the GPD is capable of detecting low-energy X-rays in the range of 2-10 keV and supports multiple event readouts, and the pixel chip can read out photoelectron signal events with the count rate up to 15

Keywords

ROIRC, Topmetal-L, LPD, pixel chip, X-ray

INTRODUCTION

POLAR-2 is the next-generation space station mission for the Chinese POLAR experiment, which is based on the same Compton scattering measurement principle as POLAR, but

with an extended energy range and an order of magnitude in- 5

crease in total effective area for polarized events [ ]. The Low Energy X-ray Polarization Detector (LPD) is one of the three payloads in the POLAR-2 experiment [ ]. LPD is specifically designed to observe the polarization of Gamma-Ray Burst (GRB) prompt emission in the energy range of 2-10 keV and to measure the polarization of the GRBs as well as their very early X-ray afterglow, both in terms of polarization degree and polarization direction [ ]. This observation is achieved using an array of X-ray photoelectric polarimeters based on GPD [ Pixel chips have excellent characteristics in terms of pho- toelectron track imaging, fast time response and high spatial resolution. Given their wide application in space exploration, the anode pixel readout chip is one of the core devices [ ]. Pixel chips typically consist of two parts: the pixel array

and the readout circuit. The readout circuit significantly im- 21 22

pacts the performance of the pixel chip. Therefore, the read- out design of pixel chips has been the focus of a series of studies. Typical readout designs of pixel chips, such as the ALPIDE chip, are applied in the ALICE ITS experiment at

This study is supported by the National Key Research and Development Program of China (No. 2024YFE0110101, No. 2020YFE0202002) and in part by the Self-Determined Research Funds of Central China Nor- mal University (CCNU) from the Colleges’ Basic Research and Oper- ation of Ministry of Education (MOE) under Grant 30106250134, and this work is supported by the National Natural Science Foundation of China (Grant Nos.12027803,U1731239),the Natural Science Foundation of Guangxi (ZY24212021).

the Large Hadron Collider at CERN. The pixel chip readout of ALPIDE employs a hit-driven fashion, reading out only the pixels that are hit by particles. The in-pixel multiple-event is read out asynchronously by the priority encoder circuit in each double column. This design is not only fast in response but also power efficient, as the expected occupancy is low, and only hit pixels are read out in a hit-driven fashion [ ]. The Imaging X-ray Polarimetry Explorer (IXPE) and the Enhanced X-ray Timing and Polarimetry (eXTP) mission uti- lize self-triggering XPOL pixel chips. Within the chip, every

2 × 2 pixel array forms a trigger mini-cluster. When a mini- 37

cluster is triggered by the signal event, the core logic identi- fies all such clusters and defines the surrounding Region of Trigger (ROT). It then defines the region of interest (ROI) for event capture and readout by adding a predefined padding on the four borders [ ]. In the XPOL-III, the approach to

ROI definition has been upgraded, which delivers enhanced 43

flexibility. This not only reduces the number of pixels within the ROI but also effectively shortens the readout time for sig- nal events [

The electronics system for the cosmic X-ray polarization 47

detection (CXPD), which functions as a prototype detector for the LPD, employs the Topmetal-II chip for its anode readout and has successfully demonstrated on-orbit capture of photoelectron signals [ ]. In the CXPD, the gas mi- crochannel plate (GMCP) and the Topmetal chip constitute the complete detection system. The GMCP is responsible for electron multiplication, offering high-precision time and energy resolution, while the Topmetal chip implements sig- nal event acquisition, position resolution, and photoelectron track imaging. The successful operation of CXPD has de- termined that the Topmetal series of chips will be used as the anode readout for GPD in the LPD. The readout mod- ules of these chips employ the rolling shutter scheme, which operates by sequentially reading out every pixel regardless of whether it has been hit by the signal event. Consequently, the

frame refresh time increases with the size of the chip array.

For the large-array Topmetal-M1 and M2 chips, the array is divided into 16 channels for parallel readout to enhance the readout rate; each readout channel requires the use of high- power analog buffers to drive signals, thereby leading to the

significant increase in the overall power consumption of the 68

chips [ ]. Compared to CXPD, the pixel chips in LPD require key characteristics such as high effective area, high count rate, and low power consumption. Therefore, large- array pixel chips that use the Rolling Shutter readout mode struggle to meet the application requirements of the LPD ]. Consequently, a novel readout scheme needs to be developed based on previous generations of Topmetal chips.

This paper presents a novel readout scheme, the Region- of-Interest Readout Circuit (ROIRC), which comprises the

scanning module and the co-processing module. The scan- 78

ning module serves as the readout circuit for the pixel chip 79

Topmetal-L, which is integrated into the LPD design. The co-processing module is implemented in the front-end FPGA.

The ROIRC is designed to rapidly identify pixels hit by sig- nal events and designate them as high-priority readout ar- eas, thereby reducing the waiting time for event readout.

The ROIRC method for determining priority readout areas 85

is implemented through the FPGA in the electronics, with- 86

out the need for comparators to perform threshold compar- isons, thereby simplifying the analog circuit architecture of

the pixel unit. Furthermore, it enables the entire readout logic 89

to function with only a single readout channel. This approach meets with the LPD requirement for low-power design in pixel chips. The proposed ROIRC scheme has been imple- mented and successfully validated through tests.

TOPMETAL-L READOUT MODULE DESIGN

Topmetal-L is a large-area CMOS pixel sensor chip de- signed for LPD. It is based on the Topmetal-II Topmetal-M chips and fabricated using GSMC 130 nm CMOS process. As shown in Fig. and Fig. , the total size of the Topmetal-L chip is 17 mm 24 mm, including a pixel matrix of 356 (row) 512 (column) with the periphery cir- cuit. The readout circuits are placed at the left and bottom of the pixel matrix. All the IO pads are located at the left, right and bottom of the chip to make it easy to be assembled in multi-chip applications. The total size of each pixel sen-

sor is 45 × 45 um 2 and the exposed noninsulated area is 26 105

. Each Topmetal is surrounded by a guard ring with the same metal layer, which is covered by an insulating layer. The coupling capacitance between the guard ring and the top metal can be used for pixel performance calibration.

The guard ring of each pixel can be biased with an external voltage signal to emulate the electrons generated by particle hits.

As shown in Fig. 3 [FIGURE:3] , each pixel unit consists of a Topmetal 113

sensor, a charge sensitive amplifier (CSA), a two-stage source follower circuit, and row readout selection switches.

Topmetal working principle is based on a patch of the topmost metal layer acting as a charge collection electrode, placed in each pixel cell and the Topmetal sensor is connected directly

to the CSA. The Topmetal sensor of the pixel unit is responsi- 119

ble for collecting charge signal and converting it into voltage signal through the CSA for amplification.

The CSA consists of a folded cascode operational ampli- fier, a feedback capacitor ( ), and a discharge transistor ). The folded cascode architecture provides high gain and superior linearity, as shown in Fig. . The feedback capacitor 1 fF), formed by the parasitic capacitance between two metal layers. The charge-to-voltage conversion gain of the

CSA is ∆ V out /Q in = − 1 /C f , where Q in is the input charge, 128

is the output voltage. The decay time constant of the CSA output signal is given by , where represents the equivalent resistance of . By adjust- ing the gate voltage of , the value of can be modified, thereby controlling the decay time of the output signal. Thus,

the Topmetal-L chip employs the decay-based mechanism for 134

pixel circuit reset. This design ensures that charge collection within each pixel remains continuous and independent of the operation of the row and column selection switches. How- ever, this architecture requires that the row and column selec- tion switches can rapidly and precisely locate the pixel region hit by the signal event. As shown in Fig. , the single pixel response to a particle signal is depicted. Upon charge deposi- tion, the sensor output exhibits a rapid step increase, followed by an exponential decay. The -axis shows the relative decay time, while the -axis indicates the output signal amplitude.

Time 1 5 represent readouts of the signal at different in- stances. 5 correspond to different signal ac- quisition moments, which are controlled by the readout logic strobe.

The CSA output is processed through the two-stage source follower. The signal is read out via row and column switches.

In each column, all row-selection-switch outputs are con- nected to the column-selection-switch. Analog outputs from the pixel signal are transmitted out by the analog buffer. The relevant parameters of the Topmetal-L chip are summarized

Parameters Topmetal-II Topmetal-M1 Topmetal-L Chip Size [ Pixel Array Pixel Density [pixels/ Power Density [W/ ENC [e Readout Mode Rolling Shutter Rolling Shutter ROIRC Readout channel Pixel Gain [ Frame rate 2.6 ms/ frame 1.2 ms/ frame 0.7 ms/ frame in the Table . As detailed in [ ], these parameters were both theoretically derived and systematically verified through mea- surement. The following discussion will focus on the readout circuit design of the chip.

The readout circuit of the Topmetal-L chip, serving as the

critical component of the ROIRC i.e., the scanning module, 158

is implemented using the standardized digital ASIC process.

This L-shaped scanning module, embedded in the lower left 160

corner of the pixel chip, manages data readout. Compared to the Rolling Shutter readout circuit, the advantage of this de- sign lies in its ability to adjust its working method through multiple sets of parameter configurations, thereby offering

flexibility and diversity in scanning schemes. The scanning 165

module employs serial input of multi-bit data for each param-

eter configuration. The scanning logic, parameter configura- 167

tion logic operate on independent clocks. This approach al- lows for customized design of different logic blocks to meet their specific timing requirements. The row readout selec-

tion switch of the pixel unit, the chip-level column readout 171

selection switch, and the control of the column start switch

are all connected by the scanning module. It achieves tim- 173

ing convergence under the 50 MHz clock constraint for both

the scanning logic and data configuration logic. However, 175

the scanning logic clock frequency is also limited by the ana- 176

log circuit, i.e., whether the analog signals of pixels before

switching can be read out within the constrained scanning 178

logic clock period. This is due to the limitation caused by the routing of large-array pixel chips, and we will focus on investigating this issue in subsequent chip iterations. In the

ROIRC testing, the 10 MHz scanning clock was utilized in 182

pixel chip testing. The function of each parameter is shown in the Table The pixel switching time is 100 ns, the data configura- tion time shift is 20 ns, the data configuration time is 20 ns per bit. Each parameter configuration consists of a 10-bit se- rial data and two enable load bits. The time required to com- plete one data configuration is 220 ns. Input signals for

the scanning module are supplied by the co-processing mod- 190

ule, whose circuit functions are implemented in an FPGA.

This FPGA-based design provides ROIRC greater flexibility and adaptability, enhancing compatibility with various low-

energy X-ray detector electronic systems. The co-processing 194

module design can also be ported to a digital ASIC implemen-

tation. The operational principles of the scanning module and 196

the co-processing module, their working relationship, and the As summarized in Table , compared to the similar pixel array in the Topmetal-M chip, the Topmetal-L requires only a single readout channel to implement the ROIRC readout logic, reducing the number of analog buffers to one-fifteenth of the Topmetal-M. Simulation results show that the operat- ing current of the analog buffer in a single readout channel is 10 mA, which effectively reduces the power consumption of the chip. Furthermore, this design enables each chip to uti- lize only one analog-to-digital converter, facilitating the low power integration of the detector system [ ]. This section primarily focuses on the circuit design from the perspective of the ASIC. The following section will present a compre- hensive overview of the ROIRC design, integrating the FPGA

within the electronics system. 212

Parameter Description CLK SHIFT Parameter configuration clock, 50 MHz.

CLK PIX Pixel scan clock, 10 MHz. ROW START IN The row start position for pixel scanning.

ROW STEP IN The row step position for pixel scanning.

ROW END IN The row end position for pixel scanning.

COL START IN The col start position for pixel scanning.

COL STEP IN The col step position for pixel scanning.

COL END IN The col end position for pixel scanning.

DATA SHIFT EN Scan parameter configuration enable.

LOAD DATA EN Configuration parameter load enable.

REGION OF INTEREST READOUT The ROIRC consists of two core components: the scan-

ning module integrated into the Topmetal-L chip and the co- 217

processing module implemented in the FPGA. The scanning 218

module receives parameters from the co-processing module,

updates the scanning configurations, and reads out the pixels 220

that have been scanned. The co-processing module is respon-

sible for determining the scanning strategy and for sending 222

control parameters to the scanning module. The scanning area 223

is determined by setting the pixel start address, pixel end ad- dress, and the number of row and column steps in the pixel array.

The ROIRC workflow consists of three sequential phases:

scanning module to perform readout at uniform row and col- 229

umn intervals. This process is defined as “sentinel monitor- 230

ing scanning”, where the pixels scanned in this process are 231

defined as “sentinel pixels”. Those sentinel pixels that are hit

ning module calculates the target area to be scanned based on 234

readout of the signal events, the ROIRC performs expands the perimeter of the area that needs to be read out; this process is defined as “region inflation”. This paper elaborates on three core components of the ROIRC algorithm. As illustrated in of rows 123–138 and columns 53–74 from the chip matrix.

The scanning module divides the parameters received from 242

the co-processing module into six distinct groups. These six parameter sets collectively define the operating mode of the

scanning module. Fig. 7 [FIGURE:7] demonstrates how the ROIRC cap- 245

tures and records the complete particle trajectory.

A. Sentinel monitoring scanning and threshold comparison 248

The sentinel monitoring scanning process is illustrated in 249

ticle events by increasing the frame rate. Sentinel pixels are

uniformly distributed across rows and columns of the pixel 252

array. Their distribution is defined by the row and column step parameters, and only these pixels are read out during this phase. The co-processing module stores the data from each sentinel scan frame. If no signal event is detected, the scan-

ning module repetitively executes this process. 257

To identify the signal event, the co-processing module compares the current frame’s sentinel pixel data with that of the previous frame. If the difference exceeds the set thresh- old, it is determined that an effective signal event has occurred around that sentinel pixel, and the pixel is identified as the trigger pixel. The co-processing module records the address information of all trigger pixels in the current frame. The time

T sen required for sentinel monitoring scanning per frame can 265

be calculated using the equation , where pixel is the total number of pixels in the array, is the number of row steps, and is the number of column steps during the

scanning process. T scan , T data are known (see more details 269

in the Section

The process of sentinel monitoring scanning. ROIRC determines the arrival of signal events through threshold comparison. readout method employing the calculation of the minimum rectangle.

The readout method employing the Block approach. The scanning module performs readout based on the Block containing the trigger pixel.

Region scanning following dilation processing.

T sen = N pixel / ( N r − step × N c − step ) × T scan + T data (1) 271

B. Region scanning 272

The region scanning scheme is executed upon the detection 273

of the trigger sentinel pixel. This scheme employs a Block-

based scanning method, where each triggered sentinel corre- 275

sponds to a predefined Block region, with the Block’s posi- tion determined by the location of the trigger sentinel. For all trigger sentinels within a cluster event, the ROIRC defines Block regions based on their relative positions: adjacent sen- tinels are assigned Blocks with boundaries strictly defined by the preset row and column interval, while sentinels identified on the event periphery can have their Block dimensions dy- namically adjusted by the co-processing module. This strat- egy integrates adjacent Blocks into a continuous readout re-

gion, thereby avoiding redundant pixel scanning while ensur- 285

ing complete event coverage.

During the region scanning process, the ROIRC reads 288

out pixel information from each Block sequentially in row- column order. As shown in Fig. , due to the large size of the chip’s pixel array, it is possible that multiple signal events hit and are detected within the duration of a single sentinel scan frame. When multiple signal events are detected within the

same sentinel scanning frame and are determined to be spa- 294

tially distant from one another (such as Block1 and Block2), the system assigns each event its own dedicated Block scan-

ning region. They are not combined into a single rectangu- 297

lar area. As shown in Fig. and Fig. 21 FIGURE:21 , compared to the

method of calculating the minimum bounding rectangle (i.e., 299

determining the coordinates of X max , X min , Y max , Y min for 300

the area), the Block-based approach reduces both the number of pixels to be read out and the associated readout time, par- ticularly for irregular or elongated tracks, as well as for tracks triggered distantly within the same frame.

The spacing between sentinel pixels can be flexibly con- figured according to the application requirements to achieve an optimal balance between frame rate and signal event cap-

ture probability. Once the region scanning is completed, the 308

ROIRC returns to the sentinel monitoring scan mode to await 309

subsequent signal events. Since the scanning module requires 310

parameter reconfiguration before each Block scan; thus, the

single-Block scanning time T block is calculated using Equa- 312

, where block is the number of pixels in a single Block.

T block = T shift + T scan × N block (2) 314

Dilation process As shown in Fig. , particle signal events typically deposit energy in irregular, spatially stochastic patterns across the pixel array. When edge signals exhibit insufficient amplitude, the difference between the sentinel frames before and after

the event may not change significantly. This prevents the sen- 320

tinel from being triggered as a trigger pixel. Consequently,

reading out only the Blocks containing the trigger pixels may 322

result in the incomplete readout of the signal event.

To resolve the issue of incomplete signal readout, the di-

lation process has been introduced into the region scanning 325

procedure in this design. The core concept is to read out not only the Block where the triggered pixel is located, but also

the surrounding Blocks containing the sentinel pixels adja- 328

cent to those triggered pixels. The size of these Blocks can be controlled by the collaborative processing module. Fig. lustrates the implementation process of the dilation algorithm. region denotes the readout time for the single signal event, where is the number of dilated Blocks, where dilation is the time required to read-out the single dilated Block.

T region = N trigger × T block + N dp × T dilation (3) 335

TEST RESULTS This section presents the test results of the Topmetal-L chip integrated into the GPD and operated under the ROIRC readout logic. The readout architecture of the pixel chip in the LPD detector must be capable of reading out complete photoelectron track images, handling high count rates, and rapidly accessing the pixel regions hit by signal events. Con- sequently, the test evaluation focuses on the readout mecha-

nism, integrity of signal events, and supports multiple event 344

readouts in this paper. It should be emphasized that the Topmetal-L chip and the ROIRC readout scheme represent only one component of the overall detection system. detector performance is influenced by multiple factors, in- cluding the internal components of the GPD, the properties

of the gas mixture, and the electronic system. Therefore, all 350

tests described hereafter were conducted under the operating conditions for both the chip and the detector, as defined in ]. This ensures that the ROIRC logic not only achieves rapid readout but also maintains the reliability and validity of the data acquired and read out by the detector. Section details the setup of the testing platform.

Test setup The experimental test platform is composed of the GPD,

an electronic system, and experimental test instruments. 359

As shown in Fig. . The GPD is divided into three func- tional regions: the electron drift region, the electron multipli- cation region, and the charge collection region. The GMCP serves as the electron multiplier in the electron multiplication region. The GMCP has the diameter of 25 , the thickness of 300 , the pore diameter of 50 , and the pore pitch of arranged in the triangular pattern, respectively, and a bulk resistance of . The drift gap between the cathode and the GMCP is 10 , and the induction gap between the GMCP and the anode is 3 . The detector was operated with the following voltages: the cathode voltage (V-drift) at 3600 V, the GMCP top surface (V-top) at

1650 V, and

the GMCP bottom surface (V-bottom) at

500 V, while the

anode was grounded. The working gas within the chamber consists of helium and dimethyl ether (DME) in the 4:6 ratio.

The energy resolution reached 18 at 6.4keV, as defined in ]. X-rays will be emitted by the Fe source or the X-ray generator. These X-rays pass through the beryllium window on the gas chamber to enter the chamber. The mixed gas in- side the chamber enhances the interaction between the X-rays and the gas molecules in the electron drift region, effectively inducing photoelectric effect and converting X-rays into pho- toelectrons. Under the influence of the electric field, these electrons drift towards the upper surface of the GMCP and enter the channels through the small orifices. Within these

channels, the cascade multiplication of the initial electrons 387

occurs, leading to the generation of a significant number of 388

secondary electrons. These secondary electrons eventually exit the GMCP and are collected by the Topmetal.

Schematic diagram illustrating the interconnections be- tween the bonding board, readout board, and FPGA core control board.

The LDO provides the power supply for the pixel chip; Amplifier-2 serves as a single-ended-to-differential converter, con- ditioning the signal for the differential-input ADC; The clock gener- ator chip (AD9517) supplies multiple independent and configurable clock signals, providing necessary timing references for the ROIRC and other digital circuits. 391

The test electronics comprise the bonding board, the read- 393

out board, and the FPGA core control board, with their in- terconnections shown in Fig. . The readout board serves two primary functions. First, it utilizes an onboard 8-channel DAC (DAC8568) chip to supply adjustable bias voltages to the Topmetal-L chip. By configuring the different DAC chan- nels, key performance parameters such as the decay time con- stant can be precisely tuned to ensure stable chip operation.

Second, the board transmits the pixel readout signals to the ADC (ADS52J90) located on the FPGA core control board.

This ADC features an input dynamic range of 2 V, the sam- pling rate of 40 MSPS, and the sampling resolution was 12 bits, resulting in the LSB of approximately 0.49 mV.

The FPGA core control board implements the co- processing module and handles data transmission and pro- cessing tasks. The exchange of control commands and data

transmission between the electronic system and the PC are 410

both accomplished via the PCIe bus interface. Furthermore, the readout board can be connected to the external oscillo-

scope for real-time monitoring of pixel output signals. Test 413

operators can inject square-wave signals into the guard ring structure of the Topmetal-L chip to simulate the injection of negative charge into the top-metal layer.

Noise testing and pixel masking As described in Section III A , the condition of “trigger pix- els” is related to the trigger threshold set in the co-processing module. However, inherent to CMOS technology, some pix- els exhibit higher noise levels than others, as shown in Fig.

If these high-noise pixels are selected as sentinel pixels, these noise fluctuations can exceed the set threshold. This causes erroneous triggering by the co-processing module, which in

turn initiates unnecessary region scanning. 425

In this test, we compared the output signal baselines of all pixels in the Topmetal-L chip across consecutive frames and visualized in binary the pixels with differences exceeding the threshold, as shown in Fig. 15 FIGURE:15 . As the threshold increases, the number of white points (pixels with differences exceeding the threshold) decreases. While the higher threshold can sup- press false triggers from noisy pixels, setting it too high risks missing valid low-amplitude signal events. To address this issue, this paper proposes implementing the bad-pixel mask- ing algorithm. ROIRC records and masks the addresses of

these defective pixels. Consequently, even if a masked pixel is designated as a sentinel, it is excluded from the trigger logic. In this experiment, conducted with no external signal injected into the chip, pixels exhibiting an inter-frame differ- ence greater than 100 mV were masked. Fig. 15(b) shows the image after masking, demonstrating that the bad-pixel mask- ing strategy effectively suppresses false triggering.

Validation of readout scheme feasibility The ROIRC detects signal events through sentinel pixels.

The spacing between these sentinels is the critical parameter, directly impacting the system’s trigger efficiency and frame rate. To optimize this, we performed the trigger rate exper- iment based on Monte Carlo simulations in the low-energy spectral region (3 keV, i.e., the lowest-energy X-ray attain- able from our team’s X-ray generator). As shown in Fig.

The results revealed that with the row and column spacing of 5 pixels and the trigger (as established in Section bad-pixel filtering), the chip achieves a collection efficiency exceeding 90 for 3 keV photoelectron signals. Based on this result, the following parameters were adopted: the row and column start address was 0, with end addresses at 355 and 511; the step size for both rows and columns was 5 pix- els; each Block corresponding to a sentinel pixel contained

25 pixels, the dilation range is set to 7 pixels; the minimum 461

scanning region (triggered by the single sentinel) of 361 pix- 462

els; and the trigger threshold was set to 200 ADC counts. In practical testing, the performance of the ROIRC scheme was validated using the Fe radioactive source, which emits mo- noenergetic 5.9 keV X-rays. This experiment assessed the detector’s capability to record photoelectron tracks under the ROIRC scheme. The test platform is shown in Fig.

Fe test platform.

( ① ) shows the sentinel scanning process, where the 470

evenly spaced blue dots represent the readout values during

sentinel monitoring, with all other pixel values set ADC value 472

to 0, and the red wireframe encloses the triggered sentinel pixels. Fig. 16 FIGURE:16 ) shows the event signals from the re-

gional readout, while Fig. 16(a) ③ provides a magnified view 475

of these event signals. Fig. 16(b) shows the sentinel pixels information at the local position of the pixel chip. Each read-

out sentinel pixel is evenly spaced and uniformly distributed. 478

The scanning region in Fig. 16(b) ② corresponds to the posi- 479

tion of the triggered sentinel pixel in Fig. 16(b) . Fig. 16(c)

demonstrates that in one single frame of sentinel monitoring 481

scanning, ROIRC can support the triggering of multiple sen- 482

tinels and perform multi-region readout operations based on the sequence of trigger pixel positions. Fig. shows the dis- tribution of the number of pixels hit per single photoelectron event from the Fe source in the Topmetal-L sensor.

According to Equation. , Equation. and Equation. , un-

der the scanning step of 5 pixels in both row and col- 488

umn directions, the maximum dead time required for read- ing effective event signals is 709.24 us. In contrast, under the Rolling Shutter readout mode, the maximum dead time

reaches 18227.2 us. During the region scanning, the extent 492

of the pixel region read out is defined by the count of trig- gered sentinel pixels. Statistical results reveal that most sig- nal events triggered only one sentinel pixel, and at most two.

Therefore, the corresponding number of pixels in the region

scanning ranges from 361 to 456. Based on this, the required 497

readout time for the single Fe event during the region scan-

ning stage ranges from 36.1 us to 45.6 us. 499

Readout signal imaging and track completeness The pixel chip is required to image the captured photoelec- tron tracks in the LPD. Thus, we must ensure that the chip reads out each signal event in its entirety. To verify this, we performed the track integrity analysis on the signal events col- lected. In Fig. , pixels marked in red indicate the triggered sentinel pixels. Their address information enables the back-

end data processor to define the scanning region. In the read- 507

out logic, all sentinel pixels are positioned at the center of their respective Block regions.

By locating sentinel pixels, the data processing can deter- mine whether the entire trajectory of the signal event is within

the scanning region, thereby confirming whether the signal 512

event has been fully read out. We conducted comprehensive analysis of track integrity for both X-ray signals and the sig- nals from high-energy alpha particles. These alpha particles are produced by the natural decay of trace amounts of radon (Rn) in the gas mixture of the GPD (This type of signal event was not statistically analyzed in the graphs of Fig. , but has been jointly validated in this section). Their high energy re- sults in more spatially expansive tracks, which consequently provides a more stringent test of readout completeness during

region scanning. As described above, the signal tracks col- 522

lected in section were analyzed, and it was verified that the trajectories of all signal events were completely read out.

ROIRC uses the Block-based readout to capture signal events of various track shapes and pixel coverage. Even if multiple event signals are triggered in one single sentinel

scanning, the readout logic ensures all signal events are read 528

out during the subsequent regional scanning. Fig. 21(a) 529

shows that particle tracks from Fe signals, and Fig. 21(b) shows tracks from alpha particle signals. 21(c) illus- trates the simultaneous generation and reading of both signals

during the same sentinel scanning period. As indicated in 533

, the black wireframe indicates the pixel area (com-

posed of all sentinel pixels’ Blocks) during region scanning. 535

Readout rate One of the primary goals of the ROIRC design is to enable the low-energy polarization detector (LPD) equipped with the large-array pixel chip capable of meeting the requirements of astrophysical observations. For instance, the peak photon count rate of GRB 221009A, the brightest GRB observed to date, reached about 4500 ph in the 2 10 keV band within a one-second interval. Considering the detection efficiency of the GPD is approximately 0.1, the signal event rate to be processed by the corresponding front-end electron- ics system is no less than 450 counts As described in section , the signal amplitude acquired by the Topmetal-L pixel chip decays over time; failure to read out the signal within this decay window results in signal loss.

Therefore, under the parameter configuration established in Section , the signal event count rate of the detector in the ROIRC readout logic needs to be evaluated. This rate

defines the number of events the chip can process per unit 553

time. In this counting experiment, the bias voltage settings for the Topmetal-L chip were consistent with those in [ ]. Based on combined simulation and experimental results, the typical discharge rate of the CSA for charge signals under this system configuration is approximately 37.28 mV/ ms. The measured counting rate of the pixel chip as a function of the X-ray tube input current for 5.40 keV X-rays in a 40 He + 60 gas mixture at 1 atm.

As shown in Fig. , which depicts the test platform, the chip is placed within the GPD. By adjusting the intensity of the X-ray generator, we can alter the quantity of signal events. eas with higher brightness indicate a greater number of signal events passing through those regions. All events were suc- cessfully read out by the Topmetal-L chip.

The test results are shown in Fig. . The Y-axis is defined as the number of signal events collected and read out by the Topmetal-L chip embedded in the GPD. The X-axis is defined as the relative intensity setting of the X-ray generator. Under the ROIRC readout mode, when the signal events count rate is less than 15 ,the chip count rate scales linearly with the increasing photon output from the X-ray generator,

meaning there is no signal event overlap. However, when 576

the signal event count rate exceeds 15 , the count rate no longer increases linearly, and some events will over- lap. These results confirm that the ROIRC operated detector achieves a maximum usable readout rate of 15 exceeding the 450 counts requirement set by the brightest known GRB scenarios.

The X and Y-axis represent the number of pixel array rows and columns. The color bar on the right represents the signal intensity in ADC counts.

CONCLUSION

This paper has presented the design and testing of the novel readout scheme, the Region-of-Interest Readout Cir- cuit (ROIRC), for the Topmetal-L pixel chip. ROIRC is im-

plemented by the digital ASIC (the scanning module) and the 587

FPGA (the co-processing module) in the electronics. We have 588

detailed its design structure, logical working principle, and functional behavior. Additionally, we have introduced test results, which include X-ray tests based on the radioactive el- ement Fe and the X-ray generator.

The scanning module is integrated into the Topmetal-L 593

chip. It receives parameters from the co-processing module,

which it uses to update the scanning configuration and read 595

out the scanned pixels. The co-processing module, imple-

mented in the FPGA, determines the scanning strategy and 597

sends the corresponding control parameters. Together, they enable a rapid and complete readout of signal events through

a two-stage process: sentinel monitoring followed by region 600

scanning. 601

Under the ROIRC operating mode, the GPD can detect Feng ZK, Liu HB, Feng HB, et al., In-orbit Background and Sky Survey Simulation Study of POLAR-2/LPD. Nat.

Rev. Phys. , 87 (2023). 4357/acfc43 Topmetal-L: noise charge-sensitive pixel sensor POLAR- 2/LPD. arXiv 2511.09863v1 (2025).

Feng HB, Liu HB, Xie YJ, Spectral and polarimetric char- acterization of the Gas Microchannel plate Pixel Detector.

J. Instrum. , P08012 (2023). 0221/18/08/P080125 Yi DF, Liu Q, Ma RT, Wang BL, Liu HB, Xie F, Feng HB, Feng ZK, Zheng YH, Star-XP: A simulation framework for Polar-2/ low energy X-ray polarization detector. Softw. X. , 101626 (2024).

Piran physics gamma-ray bursts. Phys. (2005). Berger Short-duration gamma-ray bursts.

Annu. Astron. Astrophys. (2014). astro-081913-035926 Xie Y, Liu H, Feng H, et al., Variably polarized X-ray sources for LPD calibration. Exp. Astron. , 499-515 (2023) Feng H, Liu H, Wang D, et al., Gas microchannel plate-pixel detector for x-ray polarimetry. Nucl. Sci. Tech. , 39 (2024).

P. Delpierre, A history of hybrid pixel detectors, from high energy physics to medical imaging. JINST , C05059 (2014).

L. Fan, S. Guo, Y. Shi et al., Efficiency calibration of solar X-ray detector onboard MSS-1B satellite. Nucl.

Tech. 090401 (2023). low-energy X-rays in the 2 10 keV range. The Block-based readout mode enables multiple events detected within the sin-

gle frame of sentinel scanning to be read out in different 605

regions, which effectively reduces the scanning of invalid 606

pixels. When the signal events count rate is less than 15 , the readout rate of ROIRC for signal events in- creases linearly, this result meets the application requirements of the LPD. Due to the flexibility of ROIRC, its operating modes are diverse, making it particularly suitable for scenar- ios where pixel chips require large scale assembly, low power consumption, and large detection areas.

Huang X, Liu H, Zhang J, et al., Simulation and photoelectron track reconstruction of soft x-ray polarimeter. Nucl. Sci. Tech. , 67 (2021).

[12] Costa E, Soffitta P, Bellazzini R, et al., An efficient 653

photoelectric x-ray polarimeter for the study of black holes and neutron stars. Nature 662-665 (2001).

Wang H, Wang D, Li M, et al., Low-Energy X-Ray Polarization

Detector Detection Unit Prototype. IEEE Trans. Nucl. Sci. 71 , 658

2578-2587 (2024).

[14] Rossini M, Readout chip for the cms pixel detector upgrade. 660

Nucl. Instrum. Methods Phys. Res. Sect. A , 209-213 (2014).

Y. Zhou, Y. Lu, Z. Wu et al., Highly compact digital pixel structures developed for the CEPC vertex detector. Nucl. In- strum. Methods Phys. Res. Sect. A , 164427 (2020).

ATLAS Collaboration, The ATLAS experiment at the CERN large hadron col- lider. JINST , S08003 (2008). 0221/3/08/S08003 S. Dong, P. Yang, Y. Zhang et al., Design and charac- terisation of the JadePix-3 CMOS pixel sensor. Nucl. In- strum. Methods Phys. Res. Sect. A , 167967 (2023).

Szczepankiewicz A, Readout of the upgraded alice-its. Nucl.

Instrum. Methods Phys. Res. Sect. A , 465-469 (2016).

[19] Rossini M, Readout of tpc tracking chambers with gems and 678

pixel chip. Nucl. Instrum. Methods Phys. Res. Sect. A 173-184 (2008).

Aglieri Rinella G, The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System. Nucl. In- strum. Methods Phys. Res. Sect. A , 583-587 (2017).

[21] Baldini L, Barbanera M, Bellazzini R, et al., Design, construc- 685

tion, and test of the Gas Pixel Detectors for the IXPE mis- sion. Nucl. Instrum. Methods Phys. Res. Sect. A , 102628 (2021).

[22] Bellazzini R, Spandre G, Minuti M, et al., Direct read- 689

ing of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50um pitch. Nucl. In- strum. Methods Phys. Res. Sect. A , 552-562 (2006).

[23] Bellazzini R, Spandre G, Minuti M, et al., A sealed 694

gas pixel detector for x-ray astronomy. Nucl. Instrum.

Methods

Phys. Sect. (2007).

[24] Minuti M, Baldini L, Bellazzini R, et al., XPOL-III: A new- 698

generation VLSI CMOS ASIC for high-throughput X-ray po- larimetry. Nucl. Instrum. Methods Phys. Res. Sect. A 167674 (2023).

[25] Wang H, Wang D, Chen R, et al., Electronics system for the 702

cosmic x-ray polarization detector. Nucl. Sci. Tech. (2023).

[26] Fan Z, Liu H, Feng H, et al., Front-end electronics of cxpd for 705

measuring transient x-ray sources. IEEE Trans. Nucl. Sci. 1507-1513 (2023).

Zhou Z, Zhou SQ, Wang D, et al., Low-noise and low-power pixel sensor chip for gas pixel detectors. Nucl. Sci. Tech. 58 (2024).

Liu J, Zhou Z, Wang D, et al., Prototype of single-event effect localization system with cmos pixel sensor. Nucl. Sci. Tech. 136 (2022).

Ren W, Zhou W, You B, et al., Topmetal-M: a novel pixel sensor for compact tracking applications. Nucl. In- strum. Methods Phys. Res. Sect. A , 164557 (2020). low-noise pixel direct charge sensor, topmetal-ii-. Nucl. Instrum.

Methods

Phys. Sect. (2016). Zou S, Fan Y, An M, et al., Test of topmetal-ii- in

liquid nitrogen for cryogenic temperature tpcs. Nucl. In- 723

strum. Methods Phys. Res. Sect. A , 275-278 (2016).

Gao C, Huang G, Sun X, et al., Topmetal-ii-: a di- rect charge sensor for high energy physics and imag- applications.

Instrum. C01053 (2016).