Preamble

Design verification precision system SXFEL Chengcheng Xiaoliang Chenyu Jianhao Cheng Wencheng ,Yiming

1 Shanghai

Advanced Research Institute, Chinese Academy Sciences, Shanghai 201204, China

2 Canada

particle accelerator centre Vancouver, Canada

3 Shanghai

Institute Applied Physics Chinese Academy Sciences, Shanghai China

4 University

of Chinese Academy of Sciences , Beijing 100049 , China

words SXFEL LLRF, VM,ZYNQ

Abstract

high-performance low-level radio frequency (LLRF) control system based MPSoC platform developed digital intelligent upgrade Shanghai X-ray Free-Electron Laser (SXFEL). system integrates eight 16-bit, 310-MSPS analog-to-digital conversion channels 16-bit, 500-MSPS digital-to-analog conversion channels, supporting continuous-wave pulsed operation modes.

FMC-LPC interface enables direct interoperability White Rabbit timing control network, allowing real-time feedback electron orbit, focusing, energy variations.

Experimental

results

SXFEL facility proposed system achieves amplitude stability better 0.03% (RMS) phase stability better (RMS) output pulse compressor, demonstrating capability stringent stability requirements modern facilities.

1. Introduction

Shanghai X-ray Free-Electron Laser (SXFEL) advanced X-ray free-electron laser facility driven radio-frequency linear accelerator[1]. designed operate across X-ray spectral range, providing temporal spatial coherence, brightness, ultrashort pulse durations, continuously tunable wavelengths, making powerful platform frontier research X-ray science related applications[2]. 2021, SXFEL achieved free-electron laser amplification wavelengths fully covering water window spectral region. particular, saturation obtained power exceeding MW[3], coherent radiation reliably delivered experimental endstations, marking significant advancement facility performance operational maturity[4].

SXFEL linear accelerator consists X-band, eleven C-band, X-band accelerating units[5], illustrated stability measurements injector delivered relative energy stability 0.01%, while stability linac reached 0.03%. ongoing modernization intelligent upgrade

program, stringent performance targets defined, including inter-bunch timing consistency digitized timing system within temporal resolution better digitized holographic diagnostic system. fulfill these requirements, low-level (LLRF) control system incorporate White Rabbit timing interface ensure phase-locked synchronization tight coordination global timing network.

Beyond precise timing synchronization, digitalization facilities requires robust real-time offline

analysis

frameworks. These capabilities enable continuous diagnostics, online optimization radiation characteristics, responsive feedback control, enhancing experimental efficiency stability.

However, these advancements impose demanding requirements computational performance throughput control hardware necessitate advanced algorithmic optimization achieve real-time, deterministic control under high-bandwidth operating conditions.

Layout SXFEL LINAC

2. System

Design intermediate frequency signal generated digital board output through distinct approaches: vector modulation frequency up-conversion[6]. up-conversion method, components modulate signal[7].The modulated signal mixed signal up-convert range. process expressed

Where ω RF = ω c + ω IF .

frequency upconversion

method

offers superior isolation enhanced flexibility achieving higher frequency outputs.

However, approach necessitates additional hardware, mixers filters, perform up-conversion process.

Furthermore, introduce undesirable effects, including increased noise, phase distortion, spurious signal generation, which impact overall system performance[8].

signal directly generated combining components signal. process mathematically represented

) ω sin( ) ( ) ω cos( ) ( ) ( C C t t Q t t I t S RF - = (2)

Where modulating signals, angular frequency carrier signal.

Direct facilitates precise control amplitude phase, making particularly suitable applications demanding stability accuracy.

Additionally, absence upconversion stage simplifies system architecture, reducing complexity signal distortion.

Therefore, output selected signal modulation ensure optimal performance reliability.

Shown newly developed low-level control system composed front-end frequency conversion electronics, Clock Local Oscillator(LO) generator digital processing boards, designed achieve precise reliable control microwave signals. front-end frequency conversion electronics responsible down-converting various collected microwave signals, forward reflected signals solid-state amplifiers klystrons, forward reflected signals input output accelerating structure, intermediate frequency (IF).

These signals digitized high-resolution, high-sampling-rate digital boards[9].

Within digital boards, digitized undergoes series computational processes, including calibration, proportional-integral control, phase amplitude extraction through CORDIC algorithm, among other operations[10].

These computations produce (in-phase) signal (quadrature) signal, which front-end frequency conversion electronics. signals combined reference signal undergo vector modulation generate final low-level output signal. design ensures precision stability, meeting stringent requirements advanced accelerator systems. clock local oscillator generator designed process reference signal input through series operations, including frequency division, multiplication, mixing, filtering, amplification, attenuation, produce required clock signals.

SXFEL system, low-level control adheres four-times sampling scheme, ensuring precise synchronization signal fidelity[11]. configuration critical achieving stringent phase amplitude stability demands advanced accelerator applications[12].

STM32 Trigger Reflect ADC 9 Modulator Beam Voltage ADC 10 Mixer ADC 1 Mixer ADC 2 Mixer ADC 8 DAC 1 VM Output DAC 2 Frequency conversion board MO out

2.1 Component

selection amplitude, factor control algorithm Parameter Control Ethernet Trigger Control Interlock User Logic Average Delay Caculation & rotation Cordic ADC(1) Delay Average PHASE Caculation & rotation Cordic Delay FF TABLE Offset Vector Rotation Control PHASE FF Control Digital Processing Board Clock Timing Frequency Processing MO in LO&CLK Generator system SXFEL operates pulsed acceleration mode, where achieving stability critically depends maintaining flatness microwave field.

However, during operation, output signal low-level control system undergoes amplification through solid-state amplifiers klystrons. process introduces external perturbations, parasitic capacitance, adversely affect flatness pulsed microwave signal.

Furthermore, inherent relative jitter pulse triggering mechanism exacerbates impact waveform non-uniformities, further compromising stability mitigate these effects, precise modulation low-level control system output waveform essential ensure pulse flatness input accelerating structure.

Therefore, employ Intra-Pulse Amplitude Modulation (IPAM) modulate output waveform.

Mathematically, modulated signal represented where modulated signal, time-varying amplitude function, angular frequency carrier signal, phase.

Feedback-based modulation expressed

) ( * ) ( ) ( re t A K t A t A f D + = (4)

where desired amplitude profile, deviation desired rinciple Intra-pulse Amplitude Modulation shown figure

KLYSTRON Accelerating Structures 1/Sampling rate control KLYSTRON Accelerating Structures Principle Intra-Pulse Amplitude Modulation High-resolution digital-to-analog conversion plays pivotal modulation process, enabling adjustments required achieve desired flatness.

Based system requirements, resolution sampling exceeding selected. specification ensures capability perform high-precision modulation, thereby safeguarding stability pulsed microwave signals ultimately enhancing overall performance. selection considering SXFEL system imposes overall stability requirement 0.03%, higher resolution generally preferred. because effective number (ENOB) typically lower nominal resolution after accounting non-idealities.

However, balancing performance, cost, practical implementation considerations, resolution chosen.

Similar selection, sampling critical ensure effective operation flatness modulation feedback loop.

Given modulation, sampling exceeding preferred these stringent performance requirements.

2.2 Digital

board Schematic design whole schematic digital board shown

Schematic digital board Xilinx series architecture, modules integrated:

Processing Logic Processing System (PS), connected high-speed module functions traditional FPGA, handling acquisition transmission, while module serves processor core, responsible processing controlling output signals. design low-level digital board, module equipped dual-channel 16-bit ADCs, enabling eight-channel acquisition.

Additionally, dual-channel 16-bit integrated, where outputs signals pulsed operation after differential amplification, other directly generates continuous-wave signals. module connects various interfaces, including card, HDMI, RJ45, ports. module, memory deployed, along interface, interface, ports, network interface.

During operation, microwave signals first down-converted intermediate frequency front-end frequency conversion electronics digitized connected module. module demodulates digitized signals transfers processed module module utilizes demodulated signals typically microwave samples input accelerating structure perform vector modulation (VM), proportional-integral control, other signal processing tasks output.

2.3 Front-end

frequency converter Local Oscillator/Clock generator signals output system itself, output solid-state amplifier, output reflection klystron, output reflection pulse compressor, output reflection accelerating structure, collected directional couplers subsequently subjected down-conversion processing their pulse signals[14]. schematic Front-end frequency converter Local Oscillator/Clock generator shown Synchronization clock reference system

derived 2856/108, meaning clock signals, local oscillator signals, other related frequencies align reference. ensure compatibility existing SXFEL equipment maximize performance selected 2856/54 intermediate frequency (IF).

Given four-fold sampling, clock frequency therefore During operation Local Oscillator/Clock generator, master oscillator signal first passed through 1-to-4 power divider. divided outputs serve direct reference signals. remaining signals undergoes ninth frequency division generate signal, which subsequently filtered, amplified, split signals.

Another divided output processed through two-third frequency division, followed filtering, amplification, power division, produce clock signals.

Meanwhile, additional signal undergoes two-stage frequency division generate intermediate frequency signal. signal mixed down-converted separated portion original signal.

After further filtering amplification, system outputs local oscillator signal VM output Vector Modulator REF_N REF_P SINGLE TO DIFFERENTIAL 2856MHz 2829.556MHz 2856MHz Band pass filter Power Splitter Power splitter 10dBm 24.9827MHz 2856MHz 2856MHz 317.333MHz 2856MHz 52.889MHz 52.889MHz 317.333MHz 211.556MHz Local Oscillator/Clock generator

2.4 Vector

Modulation DSP Board Front frequency converter 2829.556MHz 2829.556MHz 2829.556MHz 2829.556MHz Power Splitter 24.9827MHz Schematic Front-end frequency converter Local Oscillator/Clock generator After signal generated digital board, signal produced through vector modulation techniques.

Vector modulation involves generating baseband signal through digital signal processing, followed conversion desired frequency using digital-to-analog converters (DACs)[15]. general mathematical representation vector-modulated output shown equation

where:I(t) in-phase quadrature components, respectively, carrier direct up-conversion, offers superior precision, greater flexibility, lower distortion, broader bandwidth, making highly advantageous technique high-performance applications.

2.5 Bunch

Retrieval integrate Bunch-ID detectors, spectrum acquisition signal tagged pulse number. defined target devices requiring Bunch-ID include diagnostic equipment various detectors. synchronization Ethernet interface connected timing switch synchronize timing signals. timing Bunch-ID encoded transmitted through interface using custom protocol. timing system supplies decoding Bunch-ID target device which integrated target device annotate data.

Additionally, Bunch-ID provide delay between free-electron laser pulse

experiment

laser pulse. enables precise synchronization alignment advanced experiments diagnostics. design process, reserved banks interface FMC-LPC connector, supporting rates Gbps. configuration ensures high-speed acquisition Bunch precise synchronization external White Rabbit timing system.

2.6 Timing

distribution high-precision mixed digital systems, clock signal determines reference timing acquisition (ADC) signal generation (DAC), directly influences overall noise level conversion process output noise viewed superposition components: intrinsic noise (e.g., quantization noise thermal noise) noise introduced clock jitter.

Specifically, clock exhibits random jitter periodic jitter (PJ), there slight timing offset between ideal sampling instant actual sampling instant, resulting amplitude error output.

Under small-signal approximation, amplitude error random jitter expressed Where fundamental frequency output amplitude. value clock jitter total output noise power approximated

where represents inherent noise. Clock phase noise manifests timing jitter, which directly translates amplitude phase errors output, ultimately degrading signal fidelity signal-to-noise practical implementations, addition selecting high-quality clock sources phase noise, careful attention power integrity isolation clock distribution network.

Ferrite beads decoupling capacitors added clock distribution chips power rails suppress high-frequency ripples electromagnetic interference, thereby reducing noise coupling clock lines.

Differential routing solid ground planes employed mitigate parasitic coupling crosstalk.

Together proper reference voltage design board-level shielding, these measures minimize impact clock input noise output quality, ensuring excellent linearity stability high-speed, high-accuracy applications. overall system design digital board low-level control applications, clock distribution chips employed ensure clock quality consistency across functional modules. first distribution supplies phase-synchronous clock signals ADCs, while second drives interface, ensuring synchronized conversion transmission. third dedicated capturing distributing external trigger input, enabling stable trigger synchronization.

Finally, fourth provides additional frequency offset through fine-tuning output clock, thereby offering flexibility subsequent control compensation tasks.

3. Hardware

design stability requirements SXFEL impose stringent performance targets system, summarized Table Characteristics Working frequency(GHz) Repetition

Amplitude stability (%) (RMS) <0.0 3 <0.0 3

Phase stability( d eg.) ( RMS) <0.0 3 <0. 06

output level(dBm) -10-10dBm -10-10dBm Table.1 Requirements system board design fabrication digital board, XCZU19EG chosen processing device primarily because comprehensive advantages resource capacity, flexible structures, support high-speed interfaces.

XCZU19EG belongs Xilinx UltraScale MPSoC family, featuring quad-core Cortex-A53 dual-core Cortex-R5 processing subsystem, along abundant programmable logic resources. single-chip solution seamlessly integrates high-speed processing, real-time control, embedded software execution.

Compared other devices family, XCZU19EG provides larger number LUTs, registers, slices, higher-bandwidth transceivers, making well-suited multi-channel, high-speed acquisition transmission. design, (16-bit, MSPS) incorporated achieve high-precision, high-speed conversion.

Because acquisition transmission ports involve width rate, meeting real-time processing requirements necessitates sufficient logic resources high-bandwidth within FPGA.

Taking example, throughput channel estimated equation below:

N × R × fs = D th (8)

sampling rate, resolution, number channels. AD9652, contains channels.

Therefore, deliver Given large flow, Performance (HPIO) XCZU19EG plays pivotal supporting high-throughput, low-latency transfer. design, connected programmable logic XCZU19EG HPIO, enabling efficient reception real-time signal processing.

Moreover, XCZU19EG provides multiple high-speed interface options, including ports remote communication connector system expansion. transceivers enable high-speed optical communications suitable long-distance, low-latency transmission.

Meanwhile, interface offers flexibility adapting various custom off-the-shelf function modules, facilitating future system upgrades expanded capabilities.

Consequently, XCZU19EG virtue integration, robust performance, flexible features enables compact, extensible, reliable digital board design, effectively meeting multi-channel, high-speed acquisition signal processing requirements project. illustrated Figure overall design layout final fabricated board presented. inputs, clock signal external trigger interfaces, outputs, routed through connectors.

layout board design Fabricated board overall design layout final fabricated board

3.2 RF

front-end frequency mixer module Shown front-end adopts separated layout down-conversion vector modulation modules reduce mutual interference maintain signal integrity between channels. functional block enclosed individual metal shielding housings, measured inter-channel isolation remains above effectively suppressing local-oscillator leakage unintended coupling.

Multi-stage low-pass filtering introduced baseband paths remove harmonic spurious products arising mixing process, which improves spectral cleanliness preserves linearity amplitude phase control. high-frequency transmission sections employ low-loss Rogers dielectric substrates, reducing dispersive effects temperature-induced phase drift, ensuring stable characteristics extended operating conditions. dedicated stabilized power distribution scheme used, separate regulation analog modulation digital control circuits, limiting ripple switching noise propagation toward sensitive analog nodes. hardware configuration provides required precision vector modulation frequency conversion systems operating high-stability accelerator environments. (a)site photo Frontend module phase jitter

Frequency Mixer/ Vector Modulator frontend module comprises eight down-conversion channels vector modulator driven DAC-generated baseband signals referenced common low-noise master source. reference signals distributed through passive matched network controlled impedance length-matched routing, relative phase between channels determined layout rather active conditioning elements. phase trims applied during calibration correct residual imbalance offsets.

Channel responses adjusted maintain uniform group delay amplitude characteristics, which allows coherent field reconstruction across channels. configuration, measured short-term amplitude stability better 0.015%, integrated phase jitter below (rms) offset range.

These values obtained under stabilized power thermal conditions using standard amplitude Allan-deviation evaluation phase-noise integration procedures, remained consistent across repeated measurements. resulting performance meets requirements high-stability operation accelerator environments.

3.3 RF

front-end frequency mixer module assembled controller shown ensure reliable thermal management during continuous operation, machined aluminum heat-spreading plate mounted directly above board, providing efficient conduction dissipating processing device, Ethernet transceiver, on-board power regulation components. board interfaced carrier high-density ribbon connector, ensuring stable high-speed digital communication consistent signal timing. interconnection between board, front-end frequency-conversion stage, vector modulation module implemented using short, phase-matched coaxial links minimize insertion preserve channel isolation. module output, cavity-type narrowband filter passband incorporated suppress residual feedthrough spurious mixing components, thereby improving spectral purity reducing interference between reference drive signals.

Assembled controller

4. Firmware

design actual firmware implementation illustrated Figure architecture, digitized baseband intermediate-frequency first through finite impulse response (FIR) filter which serves attenuate out-of-band noise spurious components while preserving desired signal bandwidth.

Mathematically, standard M-tap filter impulse response implements convolution where denotes input signal samples, filtered output. carefully designing based passband stopband specifications, stage ensures spectral shaping pre-conditioning signals subsequent IQ-based amplitude phase extraction filtered, in-phase quadrature components proceed calibration module offset mismatch compensation before reaching CORDIC (Coordinate Rotation Digital Computer) engine. digital signal processing architecture developed using Xilinx System Generator, where functional blocks implemented schematic level subsequently translated synthesizable Verilog through System Generator workflow.

Shown entire processing chain operates clock frequency identical sampling rates DACs, ensuring synchronous movement across system.

Packaged functional modules encapsulate arithmetic control logic, allowing design effort focus computational behavior timing closure rather low-level handling.

Building framework, four-stage pipelined demodulator being integrated, providing continuous quadrature baseband extraction rate. pipelined structure improves

throughput timing margins, enabling stable component output while preserving phase accuracy under high-speed operating conditions. shown 9(c), system supports multiple operating modes selected through dedicated control register. selection register accessed modified online embedded Linux environment, allowing configuration changes performed without interrupting system operation. mechanism provides enhanced operational flexibility broadens applicability controller across different machine conditions, tuning procedures, diagnostic workflows. down-conversion baseband extraction stage employs 16-bit ADC/DAC interface, which necessitates 16-stage real-time pipelined CORDIC architecture vector magnitude phase computation shown CORDIC module operates system clock producing amplitude phase outputs sampling rate.

After quantization optimization, amplitude component represented 15-bit resolution phase component 17-bit resolution, providing sufficient dynamic range downstream feedback feedforward control loops. computed I/Q-derived amplitude phase signals delivered directly higher-level control algorithms without additional decimation conversion, preserving timing determinism minimizing processing latency closed-loop system.

CORDIC provides computationally efficient means performing polar-to-Cartesian Cartesian-to-polar transformations iterative shift-and-add operations rather explicit multiplications. rotation mode, example, given initial variables predefined rotation angles CORDIC iterates according where {+1,-1} determines rotation direction amplitude phase estimation, initialize iterate until which point converges signal magnitude while represents accumulated rotation angle (i.e., instantaneous phase). computationally lightweight algorithm seamlessly integrates real-time systems, facilitating high-throughput amplitude-phase determination rotation applications control advanced digital forming.

Demodule Calibration Processor CORDIC Controller offset offset table Vector Modulation Whole irmware implementation schematic times pipeline demodulator )Modules modes (d)16-order real-time pipeline CORDIC

(e)Pulse /Bunch ID in Vivado

Firmware implementation support shot-to-shot tuning rapid recovery during commissioning, absolute stamp appended acquired amplitude phase

frame within EPICS stream. stamp synchronized White Rabbit timing network associated pulse trigger, bunch identifier, global timing markers distributed accelerator control system (shown pulse-resolved timing inserted replacing column process variables (PVs), thereby ensuring recorded diagnostic sample unambiguously mapped specific electron bunch. result, commissioning personnel perform pulse-by-pulse correlation

analysis

between field evolution performance metrics, enabling faster identification perturbations reducing required re-establish optimal lasing conditions.

Result

first low-level controller deployed system designed operation C-band accelerating structures initial commissioning stage facility. photo system

interface signal stability (d)Stability output signal pulse compressor xperimental

results

SXFEL monitoring interface, which provides real-time visualization diagnostics. displayed channels include cavity input signal accelerator section, klystron output reflected signals, output signal solid-state power amplifier. interface enables operators observe amplitude phase variations

across multiple stages chain simultaneously, thereby supporting efficient tuning system stability assessment.

results

output. shown, measured performance indicates maintains amplitude stability better 0.015% (RMS) phase stability better (RMS) These

results

confirm vector modulation stage provides sufficiently noise drift characteristics support high-precision field regulation C-band accelerating structures. measured

results

indicate amplitude stability better (RMS) phase stability better (RMS) which requirement SXFEL commissioning. low-level controller described above deployed SXFEL facility operated under conditions, supporting subsequent experiments. system maintained continuous stable operation three months

6. Conclusion

outlook high-performance digital control system developed SXFEL upgrade. system based Xilinx XCZU19EG MPSoC integrates eight 16-bit, 310-MSPS channels 16-bit, 500-MSPS channels.

Experimental evaluation SXFEL demonstrates stability, achieving amplitude phase stabilities 0.015% (RMS) (RMS) vector modulator output, 0.03% (RMS) (RMS) pulse compressor output under These

results

satisfy stringent stability requirements upgraded SXFEL. system continuous stable operation three months, confirming robustness suitability long-term accelerator operation.

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