Preamble

An 8-channel, 46-ps-precision TDC ASIC with improved vernier delay loop for STCF EMC Zi-Wei Zhao, Ran Zheng, 1, 2, Chao Liu, Jia Wang, Xiao-Min Wei, Fei-Fei Xue, Rui-Guang Zhao, and Yann Hu 1 School of Computer Science and Technology, Northwestern Polytechnical University, No. 1, Dongxiang Road, Changan District, Xi’an, 710029 Shaanxi, China Research&Development Institute of Northwestern Polytechnical University in Shenzhen, No. 45, Gaoxin South 9th Road, Nanshan District, Shenzhen, 518063 Guangdong, China An 8-channel time-to-digital converter (TDC) with high precision and linearity designed for the electromag- netic calorimeter (EMC) in the Super Tau-charm Facility (STCF) is presented. A 3-level quantization structure is employed in the proposed TDC to achieve high time resolution and wide dynamic range simultaneously. A double-edge-triggered counter characterized by the elimination of metastability is used as the first level. The second and third levels are respectively implemented with a polyphase clock sampler and a modified Vernier delay loop (VDL) with an automatic reset mechanism. Two low-jitter delay-locked loops (DLLs) with different lengths are utilized to assist in vernier measurement and polyphase clocks are also provided by one of the DLLs.

A theoretical analysis with respect to the optimal combination of DLL length and reference clock frequency is presented. The proposed 8-channel TDC was implemented using 180 nm standard CMOS process with

8 V

power supply. Under a reference clock frequency of

100 MHz

, the TDC is realized with a resolution of and a dynamic range of 2560 ns . According to the results of an experimental evaluation, the best single-shot precision was 46 ps , and good consistency was observed among all channels. The results also establish that the sliding scale technique improved conversion linearity. In asynchronous measurements, the maximum differen- tial nonlinearity (DNL) and the integral nonlinearity (INL) were less than 0.4 LSB and 0.5 LSB, respectively.

Keywords

STCF, TDC, Vernier, sliding scaled technique, high linearity

INTRODUCTION

As key components of time measurement electronics, time- to-digital converters (TDC) have attracted considerable atten- tion as a topic of active research in nuclear detection [ ] and medical imaging [ ]. The Super Tau-charm Facility (STCF) currently under construction in China is a new experimental facility for particle physics based on an accelerator with ul- trahigh luminosity [ ]. The STCF facility is equipped with multiple detectors, including an electromagnetic calorimeter (EMC) which is used to measure the energy of photons and electrons with high efficiency and high resolution. In addi- tion, sufficient time resolution for STCF EMC is also required for background suppression, gamma-neutron discrimination, and event identification [ ]. A pure CsI (pCsI) crystal scintil- lator with an avalanche photodiode (APD) readout is adopted in the STCF EMC and time stamps are acquired through a front-end readout circuit (ROC) with leading edge discrim- ination (LED) digitized with a TDC [ ]. The time resolu- tion for a full response is specified as better than 300 ps

1 GeV

energy deposits, including the optical process and the response of the APD and electronics [ ]. While the decay time of pCsI used in this experiment was as long as 30 ns the large capacitance ( 270 pF ) of the adopted APD detector

This work was supported by the National Key Research and Development Program of China under Grant No.2023YFE0206300, 2023YFF0719600; National Natural Science Foundation of China under Grant No. 12375191, 12535012, 12275218, 12341502, 12105224, 12205307; Guangdong Basic and Applied Basic Research Foundation under Grant NO. 2024A1515012141; China Postdoctoral Science Foundation under Grant No. 2023M742850; 2023 Higher Education Research Fund of Northwest- ern Polytechnical University NO. GJGZWT202301.

(Hamamatsu S8664-1010) result in considerable input noise at the front-end circuit [ ]. Given these two factors, obtaining the time precision of an ROC at an ultrahigh level is a notable challenge. For example, an ROC for APD with a time preci- sion of 270 ps has been implemented by our team [ ]. To real- ize a target time resolution of 300 ps for electronics, the TDC is expected to reach a resolution of 100 ps . Because an exces- sive number of readout channels (6732 for the barrel part and 1938 for the endcap part [ ]) are expected to be implemented in the detector, the ROC and TDC have been monolithically integrated on an application-specific integrated circuit (ASIC) for high operational efficiency. The aim of this study was to investigate the TDC ASIC suitable for multichannel integra- tion with a resolution of 100-ps or less and high linearity.

A number of time-to-digital conversion algorithms and ar- chitectures have been proposed over the past few decades.

ASIC-based TDCs can be divided into three categories [ including sampling, noise-shaping, and stochastic TDC. Al- though noise-shaping TDC is performed with multiple sam- ples to obtain a high resolution, it is not applicable here due to the requirement for real-time measurement and a high count- ing rate in STCF ECAL. Stochastic TDC is also not suitable in this application scenario because of the large die area it oc- cupies [ ]. The counter-based TDC is the simplest sampling TDC structure that has a scalable dynamic range ; however, it requires a high-frequency oscillator to realize a high resolu- tion (for example, an oscillator with 8 phases and a frequency

125 GHz

was employed to obtain a resolution of 40 ps ]). The tapped delay line is a popular and easily real- ized TDC, although its resolution is typically limited by the channel length of the transistor. The unit delay of such TDCs can be relatively fixed using a delay-locked loop (DLL) [ or phase-locked loop (PLL) [ ] to overcome the limitations of variations in process, voltage, and temperature (PVT). The front-end circuit was realized using a 180 nm CMOS process

with a

3 V

power supply to obtain better dynamic range and noise performance. As a result, given that the device is man- ufactured with the same process, developing a controlled gate with a propagation delay lower than 100 ps would be chal- lenging. Thus, using only the counter or the delay line can- not achieve our design goals. Pulse shrinking [ ] and time amplification [ ] involve sampling TDC structures with a sub-gate-delay resolution, both operating with the propaga- tion delay difference between the leading edge (rising edge) and the trailing edge (falling edge) of the input pulses. How- ever, the unavoidable mismatch of delay cells in these two TDC structures usually leads to poor consistency across mul- tiple channels. Successive-approximation TDC [ ] is an al- ternative approach for high-resolution TDC; however, a long conversion time is one of its primary drawbacks. Consid- ering its high resolution, high counting rate, and superior multi-channel consistency, the vernier TDC [ ] is con- sidered more preferrable in real-time measurements. Com- pared with the Vernier delay-line TDC, the cyclic Vernier TDC has some notable advantages in terms of area occupa- tion and conversion linearity, while lagging in terms of con- version speed [ ]. Nonetheless, the cyclic Vernier TDC can still reach a relatively high speed (i.e., a conversion rate of

67 MS

was realized in [ The Nutt method [ ] was proposed with a counter and two fine time-interpolators to obtain a high resolution ( 100 ps ) and a large dynamic range (2- s) simultaneously. The counter is used to obtain the number of clock cycles between Start and Stop events, and the start and stop interpolators are used to measure the interval between Start/Stop signals and their first subsequent clock rising edge. Then, the measured interval between the start and stop signals can be expressed as

IN = T REF + T S1 − S2 , (1)

where respectively denote the measure- ment results of the counter and the start and stop interpola- tors. A finer resolution can be realized when the start and stop interpolators are further divided into additional measur- ing levels. Another merit of the Nutt method based TDC is that it naturally implements the sliding scale technique [ which can greatly improve the measurement linearity of TDC.

In this study, we propose an 8-channel, 3-level TDC based on the Nutt method to meet the requirements of STCF EMC.

The first level was realized using a coarse counter and a sec- ond level based on polyphase clock sampler is then used to measure the time residue of the first level. The time margin of the second level is quantized using a modified Vernier de- lay loop (VDL) which serves as the finest level of this TDC.

The polyphase clocks utilized at the second level are provided by a low-jitter DLL, which performs vernier measurements in conjunction with another shorter DLL, at the finest level.

The remainder of this study is organized as follows. In Section , we introduce the overall framework and princi- ples of the proposed TDC and provide an analysis of some key parameters. The circuit designs of the proposed DLL and 3-level TDC are described in Section . The experimental setup is presented in Section along with the results of the measurements. We then conclude by summarizing our find- ings and suggesting some possible avenues for future research in Section FRAMEWORK AND ANALYSIS Framework and Principles of the Proposed TDC ROC, also called as the stop signal, is measured by another channel. The time interval between the start and stop, which is known as a timestamp, is calculated and stored off-chip.

The reference clock of the chip, referred to as , can be furnished by an integrated PLL or directly from the off- chip clock source. As shown in Fig. , DLL-1 and DLL- 2 using as the input clock are composed of delay lines with n and n-1 delay cells, respectively. The counter, as the first TDC level can be triggered by both the rising and falling edges of . The results of the counter are delivered con- tinuously to each TDC channel. The second TDC level is realized with multiphase clocks produced by DLL-1, which are fed to the clock sampler in each channel. The residual time of the second level, also known as the time interval be- tween the hit event and its subsequent polyphase clock’s ris- ing edge, is measured by the third TDC level – a VDL. The vernier measurement is carried out utilizing the slightly dif- ferent delay-times between two delay cells , which are respectively controlled by DLL-1 and DLL-2. The reso- lution of TDC is determined by the third level, and is repre- sented as given in (

Re = τ 2 − τ 1 = 1 ( − 1) 0 − 1 0

= 1 ( − 1) 0 , (2)

where f 0 denotes the frequency of Clk . The dynamic range of TDC is proportionate to the number of counter digits, which can be increased according to the limits of power con- sumption and die area [ 23 ]. We can use ( 3 ) to signify the dynamic range of this TDC in which N 1 denotes the number of counter digits .

DR = 2 N 1

Tradeoffs Among Key Parameters From ( ), it may be observed that the values of should be increased to obtain a finer resolution, which means that we should insert more delay cells in DLLs or use a ref- erence clock of higher frequency. The precision of a TDC

primarily involves two components, including quantizing and random noise. The former depends on the resolution, which can be obtained in the time domain as follows [

σ q = Re 2 √

The jitters generated from the reference clock, the hit sig- nals, and those produced by DLLs likewise worsen the pre- cision by contributing to random noise in the phase domain.

Assuming that the clock and hit signals are as clean as ex- pected, jitter mostly arises from DLLs. Figure shows how the jitter from DLLs affects the precision of TDC. The hit signal is assumed to be located between provided by DLL-1 such that a replica of delivered to the VDL for the finest quantization. The jitter generated by a single delay cell is indicated as , owing to noise from the control voltage, power supply, and substrate.

The jitter of which is also the maximum accumulated jitter of DLL-1. As shown in Fig. , the cycling occurs for times on loops corresponding to , and are output signals of VDL. Assuming that the jitters generated by the 4 cascaded delay cells in VDL are uncorrelated, the accumulated jitters are represented by ( ) and ( ), respec- tively.

σ r1 = √

σ r2 = √

At the end of cycling, are fed to an arbiter for phase comparison. Thus, the time uncertainty due to jitter can be regarded as the accumulation of and is denoted as

σ 2 r1 + σ 2 r2 = √

σ r = �

whereas the value of can be deduced with the relation be- tween

= τ 1 Re = n − 1 . (8)

The total time uncertainty or time precision of TDC is repre- sented as given below.

σ T = �

The proposed design includes a delay cell with symmet- rical current-starved structure [ ] as shown in Fig. which is characterized by almost equal rise and fall times.

To avoid reversing the phase, the cell is composed of two current-starved inverters, the propagation delays of which are controlled by the output voltage of the DLL ( If we define the toggle point for both the rising and falling edges as , the unit propagation delay in DLL-1 can be obtained as

τ 1 = V DD C L I CS = 1 0 , (10)

where denotes the parasitic capacitance on the output node of each stage, denotes the mean value of the charg- ing or discharging current through during output level switching. According to [ ], the phase noise of a delay cell is dominated by white noise, and the low-frequency noise can be neglected when the rising and falling edges are symmetric.

Figure shows the noise model of the delay cell consid- ering a positive input step in which the noise contribution of PMOS is omitted. For simplicity, the bias transistors ( in Fig. ) working in the triode region were replaced with resistors with negligible voltage drop. The input transis- tor ( in Fig. ) is assumed to be saturated for simpli- fication. Then the spectral density of output noise [ ] can be described by

inN = 8 kTγI DD − tN + 4 kT D , (11)

where is the threshold of NMOS and denotes the value of the equivalent resistor of in Fig. can be considered a constant when the bias of is fixed, we adopted the phase-noise model for the inverter proposed ] to obtain the spectral density of the delay as given below.

t d = t 2 d I 2 CS sin 2 ( ft d ) inN (12)

Jitter accumulations in the third level. (c)The simplified schematic of delay cell. (d) The noise model of delay cell. where is the statics of the random delay variable, which can be represented as

d = τ 1 2 = V DD C L 2 I CS . (13)

Then, the mean square value of can be deduced using the Wiener–Khinchine theorem [ ] as given below.

σ 2 t d = � ∞

By applying ( ), and ( ), this formula can be simplified to

σ 2 t d = kTV DD C L I 3 CS ( 2 γI CS DD − tN + 1

= kT ( 2 γV DD C L V DD − V tN + 1 R D nf 0 )

On the assumption that the jitter produced with a negative input step is equivalent to that produced with a positive input step for a current-starved stage, the jitter of this delay cell with a positive input is represented by

σ 2 0 = 2 σ 2 t d (16)

Except for , the terms in ( ) can be regarded as constants. is confined within (

100 MHz

) with respect to power consumption. For simplicity, the resolution of TDC is set to a fixed value (e. g. 45 ps ). The quantized jitter in formula ( ) is also fixed. Thus, we only need to reduce the random part of the jitter, which is derived as given ), and (

σ 2 r = (9 − 8) kT ( 2 γV DD C L V DD − V tN + ( n − 1) Re R D )

From ( ), we can understand that smaller values of mini- mize the random jitter as much as possible. Given that fixed at 45 ps , we determine that

100 MHz

=16. As a result, the ideal resolution of the proposed TDC is approxi- mately DESIGN OF CIRCUIT Delay-locked Loop The structures of the two DLLs integrated into TDC are al- most identical, as shown in Fig. , except for the voltage- controlled delay lines (VCDLs) containing different numbers of delay cells. According to this analysis, the VCDLs in DLL- 1 and DLL-2 contain 16 and 15 cells, respectively. A refer- ence clock with a frequency of 100-MHz is fed to DLL-1 and DLL-2, which operate independently and do not need to be synchronized.

The lock controller [ ] is used to prevent the DLL from false and harmonic locking events by comparing the first and several intermediate phases. The delay of VCDL is forced to range within when the lock controller is en- abled, which can also reduce the time required for the DLL to become locked. The phase detector operates in the first and last phases and determines the charging or discharging status of the charge pump. Complementary switches, dummy tran- sistors, and a wide-swing cascaded current mirror are adopted in the charge pump to improve the degree of matching be- tween charging and discharging to obtain a much smaller locked phase error. In addition, a start-up circuit is used to provide an appropriate initial value to The VCDL is composed of 15/16 cascaded delay cells and 2 dummy cells, all of which were based on a modified current-starved structure. As shown in Fig. , variable PMOS resistances ( ) and variable NMOS resis- tances ( ) are controlled by spectively, which vary in opposite directions. With appropri- ate transistor dimensions, we can obtain an output with ap- proximately equal rising and falling times across the tuning range. However, the transistor used for biasing can contribute considerable noise, so that only one bias circuit is used in the DLL and the two control voltages, , are shared by all the involved delay cells either in the VCDL or in TDC channels. The constant MOS resistances ) are employed to supply a basic working current and guarantee that the delay cell still operates when is lower than the threshold voltage of NMOS, which can prevent the DLL from being inactive.

390 ps 850 ps , which covers the expected unit delays for both two DLLs ( 625 ps for DLL-1 for DLL-2). As the control voltages are trans- ferred to multiple channels with separate distances from the DLLs, the control voltages shift variously at each channel. As shown in Fig. , we suppose that the shifts of VC1 given by DLL-1 and VC2 given by DLL-2 are both . Given the high linearity of the delay-voltage characteristics within a small voltage range, the unit delays controlled by VC1 and VC2 are both skewed by . Therefore, the resolutions of all the channels can be considered as roughly consistent, as they are dominated by the difference between these two unit delays.

First and Second Levels The first TDC level is based on an 8-bit global counter with a double-edge-triggered structure [ ] as shown in Fig.

The counting results obtained with the ris- ing and falling edges of respectively, are delivered to each channel simultaneously. The data selector in the chan- nel is used to capture the proper counting result whenever the asynchronous Hit signal arrives, according to the result of the second level 2[3 : 0] as shown in Fig. . If the asyn- chronous input signal denoted by is located in the first half of the clock cycle, we obtain 2[3] = 1 and CntN is cho- sen as the result of the first level. In the case that the curs in the second half of the clock cycle, is selected.

The implementation of a double-edge-triggered counter and appropriate settings is designed to eliminate the metastability of the counter.

One of the tasks of the second level is to measure the time interval between and the first rising edge of follow- ing the Hit, which can be realized using a polyphase clock sampler composed of 16 arbiters as shown in Fig. . An- other task is to transfer the residual time to the next level with the synchronizer. For example, if is captured by the sampler, the residual time is the time elapsed between . Although well-matched loads are inserted in both signal paths of the synchronizer, there are still er- rors between the input and output intervals. According to a Monte Carlo simulation, the maximum error was approxi- mately , which is considered tolerable because the final resolution is much larger than the error.

C. Third Level–Vernier Delay Loop

The VDL used to quantize the residual time of the sec- ond level is a modified version of that proposed in [ ], as shown in Fig. . The VDL contains 2 structurally identi- cal loops. The loop with the input named is a slow loop and that with the input named is fast.

the two outputs of synchronizer as shown in Fig. precedes and the interval between them is denoted by varies within 0 ˜ 625 ps . The edge-detection circuit is used to generate a narrow pulse when the rising edge of rives. There are 2 types of unit delays in each loop which are regulated by the control voltages provided by DLL- 1 and DLL-2, respectively. The single-delay cell and arbiter are used to convert the narrow pulse into a pulse with a width . The cycle periods are determined by the 3-cascaded delay cells in the scenario that the delays of other logic on the loop can be neglected, which are for the slow loop and for the fast loop. As shown in Fig. , signals at nodes are denoted as , respec- tively. precedes signal before cycling, and the interval between is decreased by after each cycle. The cycling stops when catches up with . The number of cycles required to align can be obtained using the pulse counter and represented as

f = ⌈ f τ 2 − τ 2 ⌉ . (18)

Ideally, the maximum is 15, for which a 4-bit counter is sufficient. However, a redundant bit is added to calibrate the measurement results.

Because the VDL is expected to measure the arrival times of sequential pulses, an auxiliary circuit that can make VDL automatically reset after quantization is included as shown in the dotted box in Fig. , where signals at nodes are denoted as , respectively. The timing diagram of the critical signals is shown in Fig.

Before quantization, the global first takes to 0 to clear all nodes in the loop, and then is pulled up to 1 to obtain a loop ready for cycling. The cycling stage of VDL begins as soon as arrives. When aligned after several cycles, the flip-flop samples are set to 1, is set to 0, and both two loops are cleared. Synchronized are successively pulled down to zero with a delay of . Subsequently, the flip-flop is cleared, and are pulled up to 1 in turn. After these steps, the VDL is once again ready for the next quantization. With this automatic reset mechanism, the maximum dead time of VDL is less than 45 ns , which implies that the conversion rate of a single channel can reach up to

5 MS

. Considering the integration and serial readout of data from the 8 channels, the overall conversion rate of the proposed TDC chip can reach

5 MS

. In addition to a fast ROC, the pileup effect in STCF EMC can be mitigated because the background counting rate

1 MHz

ASIC PROTOTYPE AND PERFORMANCE ASIC Prototype and Experiment Setups The proposed 8-channel TDC was taped out using a stan- 180 nm CMOS process with a

8 V

power supply; a mi-

crophotograph of the chip is shown in Fig. . The layout of TDC channel is designed with a strip shape, and 8 chan- nels are arranged in a column, which makes distribution paths as short as possible. The chip has a die area 55 mm 42 mm , including the pad ring.

Figure shows the experimental setup composed of an oscilloscope to observe the signal series, a spectrum analyzer for jitter measurement, 2 pulse generators to provide the ref- erence clock and input signals of TDC, an FPGA board, an upper computer for chip control, and a logic analyzer used to collect and process the measured data. We adopt a clock gen- erator chip, AD9552, to provide a

100 MHz

reference clock with a jitter below , rms. The reference clock is directly given by pulse generator in linearity evaluation.

Performance of DLL Three chips were tested and verified, which are referred to as chip-1, chip-2, and chip-3. Unless specifically indicated otherwise, all measurements described below were performed with chip-2. Two approaches were adopted to obtain the jitter of DLL. The firs was to obtain the phase noise curve of the last polyphase clock and integrate it within the frequency shift range of (

20 MHz

), and the other was to measure the jitter directly with the oscilloscope. A jitter of rms can be obtained using both approaches, which is much less than the resolution of TDC. The other performances are listed in TABLE The performance of DLLs with

100 MHz

reference clock. Jitter of the last phase (ps, rms) Duty cycle of the last phase Locked error (ps) Performance of TDC For the first, we need to determine the actual resolution (LSB) of each TDC channel. Because the bin distributions are nearly consistent over all clock periods [ ], we only need to evaluate the actual LSB within one clock period.

One channel of the pulse generator is dedicated to provid- ing the

100 MHz

reference clock, and the TDC input with a frequency of 000 01 MHz is derived from another channel.

Thus, the interval between TDC input and the rising edge of the reference clock increases by 625 ps with each clock cy- cle. This interval is cyclically repeated within the range of 0 10 ns , which can be considered as an approximate method for code density testing [ In ideal scenarios, the number of bins within the 10 ns surement range is fixed (approximately 240) with an LSB size of approximately . However, many nonideal factors can cause the actual LSB to be either larger or smaller. The tested DNL and INL values of the second TDC level across 8 channels with high consistency are shown in Fig. respectively. The nonlinearity of the second level mainly arose from mismatches of VCDL in DLL-1, which results in variable “margins” between the second and third levels. To explain this, we assume 2 types of step sizes for the second level with 600 ps 650 ps , which are also intervals to be measured using VDL. Without considering nonideal factors in VDL, the resolution was fixed at . Then, the sizes of VDL’s last VDL bins for the input intervals of 600 ps 650 ps were set to , respectively.

A bin-size filtration mechanism was implemented to pre- vent the last bin within the VDL quantization range from be- coming too narrow to worsen the DNL. First, the approximate magnitude of LSB was ascertained. If the size of the last bin was less than LSB/4, it was combined the last bin with the second-to-last bin into a new bin. Otherwise, the final bin was retained. The bin distribution of Channel-1 within a sin- gle clock period is shown in Fig. . The LSBs of eight channels after processing are presented in Fig. , which shows the approximate measured results across 3 chips. The LSB of channel-1 was larger than those of the other chan- nels, which can be explained by the significant deviation in the supply voltage in this channel.

Channel number DNL (LSB) INL (LSB) Start channel and Stop channel.

Start vs Stop DNL (LSB) INL (LSB) Ch-1 vs Ch-2 Ch-1 vs Ch-3 Ch-1 vs Ch-4 Ch-1 vs Ch-5 Ch-1 vs Ch-6 Ch-1 vs Ch-7 Ch-1 vs Ch-8 The distribution ranges of DNL and INL in each of the eight channels over a single clock period ( 10 ns ) are listed in TABLE . We also assessed the linearity in the asynchronous measurement mode, in which Ch-1 served as the start chan- nel and one of the other channels served as the stop channel.

The code density test was performed again, in which Start

(d)The actual LSBs of 8 channels across 3 chips. and Stop were provided by a single pulse generator with fre- quencies of 000 01 MHz

4 MHz

respectively. Because only the measurement results of the second and third levels are collected, the interval between the Start and Stop can be considered as randomly distributed within (0, 10 ns ) with a

100 MHz

reference clock. TABLE shows the linearity per- formance of 7 channel combinations, from which it may be

observed that DNLs better than 0.4 LSB and INLs better than 0.5 LSB were obtained for all test cases. Comparing the test results of the single- and dual-channel methods demonstrates that the asynchronous TDC inherently employing the sliding- scaled technique provides a great advantage in terms of lin- earity.

The single-shot precision (SSP) of the proposed TDC was

Ch-2. (e) Tested accuracy along TDC’s dynamic range with the combination of Ch-1 and Ch-2. (f) Specification of two cases of correlated cross-talk between Start and Stop. (g) Measured SSP curve with time intervals within (0, 249-ns), which includes the two cases of correlated cross-talk. measured in asynchronous mode. The output of the pulse generator was divided into two identical signals using a power splitter.

One was transmitted to the start channel (Ch-1) through a cable, and the other was transmitted to the stop channel (one of the other channels) through a cable, which is referred to as a cable delay measurement test [ ]. The best uncalibrated SSP of was obtained using a combination of Ch-1 and Ch-2, as shown in Fig.

The precision was improved by using the look-up table for INL [ ]. The principle of calibration is expressed as follows.

TDC CAL = TDC RAW + INL [ TDC RAW ] (19)

where denote the raw and calibrated TDC digits, respectively.

The calibrated SSP for 46 ps shown in Fig. . The tested SSPs with other channel com- binations are shown in Fig. , which are all in the range of 45 ps 70 ps after calibration. To validate the effectiveness of the calibration, we measured SSP along an input interval range of ( 10 ns ). As shown in Fig. , SSP results with different inputs become more consistent after calibra- tion. As this calibration method relying on INL results is de- signed to compensate for nonuniform LSBs, the test results can mutually corroborate this theory. Hence, the test and cal- ibration methods employed were proven to be correct. The accuracy represents the error between the input and output, which was also measured over the dynamic range of TDC as

Delay line Vernier Counter Counter Vernier Gated ring oscillator (GRO); voltage controlled ring oscillator (VCRO).

The power consumptions of all TDC channels are included.

The presented power dissipation of proposed chip is obtained with the conversion rate of 4-MS/s. shown in Fig. . Because the metastability was eliminated with the double-edge-triggered counter, no significant devia- tion in accuracy was observed in the test results.

The precision of TDC can be degraded due to the effect of cross-talk, which introduces distortion of the edges of the Start or Stop signals. Both correlated and uncorrelated cross- talk mechanisms can have an effect. Uncorrelated crosstalk is typically difficult to evaluate, and we focused more on corre- lated crosstalk [ ]. An experiment was conducted to study the effects of the crosstalk. Two adjacent channels, channel-1 and channel-2, were used to obtain timestamps of the Start and Stop signals, respectively. The input pads of these two channels are close to each other so that the effect of crosstalk on them can be more significant. The Start and Stop signals were both

4 MHz

, and the time intervals between them (de- noted as ) varied within (0, 249 ns ). As shown in Fig. the rising edges of the Start and Stop signals were distorted by each other with = 0, and the rising edge of Stop will be distorted by the falling edges of Start with 125 ns The SSP evaluations were performed at various time inter- vals. Although it may be observed from Fig. that the SSP with = 0 was significantly worse than other cases, it was not significant with the case of 125 ns speculate that this may be because the effect of crosstalk is greater when the rising edges of the Start and Stop are coinci- dent. The effects of metastability can be neglected because of the asynchronous measurement mechanism and double-edge- triggered counter of this TDC, and the degradation of SSP can be explained by crosstalk. Therefore, these instances with correlated crosstalk should be excluded from the system’s op- erating mode of TDC.

TABLE shows the comparison of the proposed TDC with others, which are all suitable for multichannel applica- tions. Compared with the delay-line structure in [ ] and the counter structure in [ ], the proposed TDC has a notable ad- vantage in terms of precision. These results show that our design exhibited superior conversion linearity in contrast to

the structures based on ring oscillators given in [ 34 ] and [ 37 ].

The TDC proposed by [ 35 ] is also based on a vernier con- trolled with dual DLLs, but it exhibited worse linearity and a slower conversion rate compared to the proposed TDC. [ 38 ] and [ 39 ] provide two TDCs based on Xilinx 7-series 28 nm FPGA, and the performance of our TDC was still competitive among them.

SUMMARY

The design of an 8-channel, high precision TDC ASIC for STCF EMC has been reported along with the results of an experimental evaluation. The proposed TDC is based on a 3-level Nutt structure that can reach a wide dynamic range and high resolution. The sliding-scale technique is employed with the proposed TDC and its role in improving the con- version linearity was demonstrated. The prototype chip was implemented using a standard 180 nm CMOS process with a die area of 55 mm 42 mm . According to the testing results, the proposed TDC features a single-shot precision of 46 ps for the best channel, DNL better than 0.4-LSB and INL better than 0.5-LSB, and good consistency among all chan- nels was observed. Moreover, it also exhibited good consis- tency in performance across all TDC channels. Considering the flexible vernier-type framework employed by this chip, our next step will be to further improve the TDC’s resolution and expand it to accommodate more channels. Synchroniza- tion and matching among multiple channels remains as an im- portant direction for future work, along with the development of methods to suppress jitter and techniques to compensate for temperature .

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