Hardware Design of an FPGA-Based Nuclear Signal Generator

Yao Yang¹,³,⁴, Xiaohui Li¹,³,⁴, Fanhui Meng¹,³,⁴, Huan Huang¹,³,⁴, Daowu Li¹,³,⁴, Long Wei¹,²,³,⁴,
Corresponding author: weil@ihep.ac.cn*

Abstract

Traditional nuclear experiments that rely on radioactive sources pose radiation exposure risks and suffer from limited experimental flexibility. To address these challenges, this study presents a highly safe nuclear signal simulator based on an FPGA (Field Programmable Gate Array) and DAC (Digital-to-Analog Converter) architecture. The device employs an all-digital hardware solution to generate nuclear signals conforming to Poisson distribution and energy spectrum characteristics, while supporting customizable waveform simulation and pile-up effect emulation. The hardware system adopts a layered design: the digital board centers on a Xilinx Kintex-7 FPGA, integrating Flash firmware storage, USB 3.0 protocol communication, SPI touchscreen control, and precision clock management modules; the analog board features dual-channel AD9764 DACs and a high-speed ADC, achieving 12-bit resolution, 125 MSPS signal output, and real waveform acquisition capabilities. This design realizes hardware integration of dual-channel independent output, touchscreen control, and network-based debugging functions, providing a zero-radiation-risk experimental platform for nuclear detector calibration and nuclear imaging electronics design, which holds significant implications for enhancing safety in nuclear technology applications.

Keywords: Nuclear signal generator, FPGA, Signal generation

¹ Beijing Engineering Research Center of Radiographic Techniques and Equipment, Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
² School of Nuclear Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, China
³ CAEA Center of Excellence on Nuclear Technology Applications for Nuclear Detection and Imaging, Beijing 100049, China

Nuclear technology represents a modern high-tech field widely applied in medicine, agricultural production, environmental protection, and numerous other domains. However, we must recognize that while nuclear technology creates benefits for humanity, it also introduces certain hazards [1]. Therefore, to ensure safety while developing and utilizing nuclear technology, we have designed a simulated nuclear signal generator to support nuclear technology advancement [2]. Compared with real radioactive sources, this device offers several advantages. First, safety: using simulated nuclear signals instead of real radioactive sources eliminates radiation risks and reduces dose exposure during experiments. Second, flexibility: real radioactive sources have limited varieties, and certain specific nuclides are difficult to obtain, whereas simulated nuclear signals allow flexible parameter adjustment to provide simulation of various radiation source types.

Research on nuclear signal simulators began in the 1950s, with early implementations using analog components that exhibited suboptimal performance [3]. In recent years, with rapid developments in electronics technology, the combination of Field Programmable Gate Arrays (FPGA) and Digital-to-Analog Converters (DAC) has become the mainstream hardware architecture. In 2017, Ponikvar developed a nuclear signal generator conforming to exponential decay characteristics [4]; Yin and Jin also developed related equipment in 2018 and upgraded it in 2024 [5,6]. Additionally, commercial products such as the CAEN DT series employ similar schemes to achieve specific energy spectrum and time distributions through parameter configuration [7]. Building upon these foundations, we have designed a high-quality nuclear signal simulator that, in addition to meeting Poisson distribution timing requirements and energy spectrum amplitude requirements, supports custom waveforms and pile-up simulation. Equipped with a touchscreen, it can operate independently without a host computer. While assisting in the design of nuclear detection and imaging electronics, this device also promotes the overall development of nuclear technology. This paper focuses on the hardware design; for firmware details and comprehensive test results, please refer to reference [8].

2. Hardware Design of the Nuclear Signal Simulator

The nuclear signal simulator designed in this paper consists primarily of a digital board and an analog board, as illustrated in [FIGURE:1]. The digital board, with the FPGA as its main chip, is responsible for implementing nuclear signal simulation algorithms and host computer communication functions. The analog board, centered on DAC chips, converts the digital signals generated by the FPGA into analog signals. The two boards communicate via Samtec board-to-board connectors.

2.1 Digital Board Design

The digital board comprises several modules. The FPGA serves as the main controller, receiving commands from either the host computer or touchscreen, performing corresponding logical or data processing, and finally generating nuclear signals. Flash memory stores the FPGA firmware program, ensuring normal operation after power cycling. The clock module provides operating clocks for both digital and analog board components. The power module supplies power to all modules on both boards. USB enables communication between the FPGA and host computer. The microcontroller facilitates communication between the FPGA and touchscreen. Detailed hardware descriptions for each component follow below.

2.1.1 Digital Board FPGA Circuit Design

FPGA is a programmable logic device—a semiconductor component whose circuitry can be reconfigured through programming. Its circuits are not fixed during manufacturing but can be programmed and reconfigured as needed during operation. This design employs a Xilinx Kintex-7 series FPGA with the following primary connections: Bank12 connects to the USB module for host computer communication, Bank18 connects to the microcontroller for touchscreen communication, and Banks 13, 15, and 16 connect to Samtec's 156-pin connector for analog board communication. Additionally, a DDR chip is incorporated for data caching, physically connected via Banks 33 and 34.

2.1.2 Flash Circuit Design

Since FPGA internal programs are lost after power-off and require reprogramming, a Flash chip is configured on the digital board. Upon each power-up, the program stored in the Flash chip is automatically loaded into the FPGA. The hardware design is shown in [FIGURE:2]. The chip operates on a 3.3V power supply, and this design utilizes four data lines for simultaneous configuration to accelerate the FPGA configuration process during power-up.

2.1.3 Digital Board Clock Design

As shown in [FIGURE:2] (Flash chip connection diagram), this project employs a clock chip to generate a 200 MHz differential clock signal that directly feeds into the FPGA's clock port. After processing through the FPGA's internal MMCM and PLL clock IP cores, multiple clocks of different frequencies are generated, among which the 125 MHz clock serves as the system master clock, meeting the requirements of the DAC and other devices. The hardware additionally uses a clock chip to generate a separate 125 MHz differential clock signal, which enters a CDCLVD1208RHDT clock buffer chip to produce three 125 MHz同源 clocks (co-sourced clocks). These three clock signals are ultimately input to the FPGA clock input port, FPGA GT module clock input port, and analog board respectively.

2.1.4 Power Supply Circuit Design

The power supply design for this project is relatively complex, generally divided into three major modules as shown in [FIGURE:3]. The first module provides power required for FPGA operation. The second module supplies power for peripheral operations, such as USB and microcontroller sections. The third module provides power for analog board operation.

As illustrated in [FIGURE:3] (Power structure diagram), the first module includes 3.3V, 2.5V, and 1.8V bank voltages, enabling different logic level standards for various banks. It also provides a 1V core voltage and 1.8V auxiliary voltage. Finally, to ensure proper GT module operation, three MGT power supplies—MGTAVCC, MGTAVTT, and MGTVCCAUC—are designed to provide 1.0V, 1.2V, and 1.8V voltages respectively. Because GT modules operate at high speeds with stringent power requirements, all MGT power supplies in this design are generated using LDO chips to ensure minimal power ripple.

The second power supply module relates to the microcontroller and USB chip, for which 3.3V and 1.2V power supplies are designed to ensure adequate power delivery.

The third module concerns the analog board. To meet the analog board's high-performance power requirements and diverse voltage needs, relevant power conversion is implemented on the digital board. DC-DC power converter chips transform the input 12V power supply, delivering three voltage levels: 12V, 5V, and -12V. The analog board subsequently uses LDO power chips to further convert these three voltages to obtain the final required power scheme. Detailed analog board power solutions are described in Section 2.2.3.

2.1.5 Digital Board USB Circuit Design

The primary communication method between the digital board and host computer is implemented via USB protocol, facilitated by the Cypress CYUSB3014-BZXI chip. The hardware design is shown in [FIGURE:4]. The USB circuit design is relatively complex: it connects to the host computer through a USB Type-C interface, while communicating with the FPGA through the GPIF II interface. The GPIF II interface includes, in addition to 32-bit data communication, control signals such as FLAGA, FLAGB, FLAGC, FLAGD, SLCS, SLOE, SLWR, SLRD, PKTEND, and PCLK. Among these, PCLK is the clock signal whose frequency determines the data transfer speed between the FPGA and CYUSB3014-BZXI chip. According to the chip datasheet, the maximum frequency for this clock signal is 100 MHz, yielding a theoretical maximum transfer rate of 100 MHz × 32 = 3.2 Gbps. However, in practical use, the actual rate is lower than 3.2 Gbps due to factors such as intervals between data packets and upstream/downstream transfer overhead.

2.1.6 Microcontroller Circuit Design

To enable standalone operation without a host computer, touchscreen control was considered during hardware design. Therefore, an external STM32 chip is incorporated to control display output. The communication connection between the STM32 chip and FPGA is shown below. The primary communication method employs two SPI interfaces: one for the FPGA to control the STM32 chip for touchscreen display output, and another for transmitting touchscreen input data from the STM32 chip to the FPGA. Additionally, 14 redundant IO connections are designed for flag bits during SPI protocol transmission to ensure transmission stability.

The STM32 chip also connects to a W5500 network chip. This chip's main function is to transmit SPI protocol data over the network to the host computer for debugging purposes, allowing observation of SPI protocol status and simulator operation status. When necessary, a small amount of data can also be transmitted from the host computer to the FPGA board through this network port.

2.1.7 Final Digital Board Circuit Design

The final digital board circuit design is shown in [FIGURE:6]. This circuit board comprises 12 layers total, including 4 ground layers and 8 signal layers. In addition to the aforementioned designs, a 156-interface connector is designed on the far right side of the board for data communication between the digital and analog boards. This connector is divided into three sections, each containing 56 pins, with each section connected to one FPGA bank, utilizing three banks in total.

2.2 Analog Board Design

The analog board centers on DAC to implement digital-to-analog conversion functionality. In this project design, two DAC chips are employed to enable simultaneous two-channel conversion. Additionally, an ADC chip is incorporated into the analog board, endowing the designed board with the capability to acquire real analog signals.

2.2.1 Analog Board DAC Circuit Design

The analog board employs two single-channel AD9764 DAC chips to form a dual-channel analog signal output, as shown in [FIGURE:7]. The AD9764 is a single-channel high-speed 14-bit DAC that operates normally simply by inputting the DA conversion clock frequency at the CLOCK port, with rates up to 125 MSPS. The left-side DB0-DB13 are digital signal input ports, connected to FPGA Bank13 via the Samtec interface. The right-side IOUTA and IOUTB are analog signal outputs (in current form), which are subsequently converted to more通用的 voltage signals through AD8047 chips.

2.2.2 Analog Board ADC Circuit Design

Analog-to-digital conversion functionality (ADC) is not inherently required for a nuclear signal simulator. The ADC is included in this design solely to facilitate acquisition of actual nuclear signals. Real nuclear signals can be acquired through the ADC, saved as data in the host computer to establish a real waveform database. When needed, appropriate signals can be selected from the waveform library and sent back to the FPGA for use as custom waveforms. The ADC circuit connection diagram is shown below. Its concept is opposite to that of the DAC: the two Ain ports on the left input analog signals, which are finally converted to digital signals and transmitted to FPGA Bank15 via D0-D11 to implement waveform sampling functionality.

2.2.3 Analog Board Power Supply Circuit Design

Compared with digital boards, analog circuits are more susceptible to noise interference, requiring lower ripple and noise in the analog board power supply. The analog board power supply uses LDO chips to further convert the voltages output from the digital board, as shown in [FIGURE:9]. As mentioned in Section 2.1.4 (Figure 3), the digital board outputs 5V, 12V, and -12V voltages. The analog board converts the 5V voltage into two 3.3V supplies, used as digital 3.3V and analog 3.3V respectively. The 12V voltage is converted to 5V for use as analog 5V power to supply the ADC chip. The -12V power output from the digital board is converted to -5V power for the AD8047 current-to-voltage amplifier chip.

2.2.4 Final Analog Board Circuit Design

The final analog board circuit design is shown in [FIGURE:10]. This circuit board comprises 6 layers total, including 2 ground layers and 4 signal layers. In addition to the aforementioned designs, a 156-interface connector is designed on the far left side of the board, corresponding to the digital board's 156 interface, for data communication between the digital and analog boards.

2.3 Final Circuit Board Design

The final assembled circuit board is shown in [FIGURE:11], comprising both digital and analog board sections. The digital board primarily handles communication and algorithmic processing, while the analog board is responsible for analog-to-digital and digital-to-analog conversion functions.

5. Hardware Testing

For firmware and software test results, please refer to reference [8]; this section focuses on hardware test results.

5.1 Hardware Testing

Hardware testing primarily includes ground resistance, power supply output voltage, and clock frequency tests. [TABLE:1] shows the ground resistance test results. All resistance values are normal with no short circuits, indicating the board can be powered on for subsequent testing.

[TABLE:1] Ground Resistance Table
FPGA3V3 | FPGA2V5 | FPGA1V8 | FPGA1V5 | FPGA1V0 | MGT1V8 | MGT1V2 | MGT1V0 | USB3V3 | DACBOARD_5V | DACBOARD_12V | DACBOARD_-12V | AVDD5V | AVDD3V3 | DVDD3V3
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---
Ground Resistance (kΩ)

[TABLE:2] presents the power supply output voltage test results, showing all voltages within expected ranges without overvoltage or undervoltage issues.

[TABLE:2] Voltage Output Table
FPGA3V3 | FPGA2V5 | FPGA1V8 | FPGA1V5 | FPGA1V0 | MGT1V8 | MGT1V2 | MGT1V0 | USB3V3 | DACBOARD_5V | DACBOARD_12V | DACBOARD_-12V | AVDD5V | AVDD3V3 | DVDD3V3
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---
Output Voltage (V)

5.2 USB Testing

To facilitate USB protocol testing, a dedicated FPGA USB test program was developed as shown in [FIGURE:12]. The FPGA side contains three modules: a data generation module that produces continuously incrementing integers with each clock cycle, a FIFO for cross-clock data transfer between the data generation module and USB protocol, and the FPGA-side USB protocol module. After connecting the board to a computer, data reading tests are performed, including data integrity and data rate verification.

[FIGURE:12] Test Program Structure Diagram

The host computer test software employs Cypress receiver programs that receive data in 1024-byte packets, with each packet containing 256 data points. Starting from 0, each packet ends with 255 (FF in hexadecimal). Test results are shown in [FIGURE:13].

[FIGURE:13] USB Multi-Packet Data Results Diagram

Data rate testing employs Cypress speed test programs. Verification is performed from two aspects: first, host computer-side reception rate testing, and second, FPGA packet capture auxiliary verification. Test results are shown in [FIGURE:14]. The left image shows the host computer test rate, displaying 248,200 KBps (approximately 2 Gbps). The right image shows FPGA packet capture auxiliary verification results, where the fx3_wdb variable changes most of the time, further confirming that data is indeed being transmitted continuously.

[FIGURE:14] USB Rate Test Results Diagram

5.3 ADC Testing

ADC sampling function results are shown in [FIGURE:15]. After generating a sine wave with a signal generator, the signal is first captured using ILA on the FPGA to verify whether the digital signal input to the ADC chip is normal. The continuous sine wave display confirms normal ADC sampling function. The ADC sampling results are then directly input into the corresponding FIFO and uploaded via USB protocol. The sampled data received via USB is saved, parsed using Python, and finally displayed as an image, which shows consistency with the waveform captured by the ADC.

[FIGURE:15] ADC Sampling Results Diagram

6. Prototype Demonstration

This research has successfully developed a dual-channel nuclear signal simulator based on an FPGA+DAC architecture. Through all-digital hardware design, it achieves high-precision simulation of nuclear radiation signals and zero-radiation-risk experimental validation. The physical unit is shown in [FIGURE:16]. The front panel features two touchscreens for displaying and controlling the simulator's two channels. The bottom has three interfaces: the two side interfaces are DAC outputs, and the center interface is the ADC input. The top features a circular vent area for active cooling.

[FIGURE:16] Nuclear Signal Simulator Enclosure Display Diagram

This work was supported by the Shandong Provincial Natural Science Foundation grant ZR2022QA086.

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