Preamble

Comparative Study of Total Ionizing Dose Effects in sub-20 nm Bulk Silicon FinFET Technology at 110 K and 290 K

Hui-Bin Pi,¹ Long-Sheng Wu,¹,† Deng Luo,² Guo-Fang Yu,² Qi-Wen Zheng,³ Xin Wang,³ Xiao-Nian Liu,⁴ and Wang-Yong Chen⁵
¹School of Microelectronics, Xidian University, Xi’an 710071, China
²College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China
³Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, Urumqi 830011, China
⁴School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
⁵School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai 519082, China

This article investigates the synergistic effects of cryogenic temperatures and radiation exposure on aerospace components. Test chips were fabricated using a sub-20 nm bulk silicon FinFET process, primarily comprising ring oscillators and bandgap reference (BGR) circuits that incorporate parasitic vertical PNP bipolar transistors. Radiation experiments employed a ⁶⁰Co γ-ray source with a dose rate of 200 rad(Si)/s and a total dose of 1 Mrad(Si), comparing two temperature conditions: 110 K and 290 K.

Following a 1 Mrad(Si) irradiation, chip #1 maintained at 290 K exhibited a 113% increase in leakage current relative to its fresh state. In contrast, chips #2 and #3, both irradiated at 110 K, demonstrated substantially larger increases in leakage current, reaching 7133% and 4248%, respectively. Post-irradiation measurements at 290 K indicated leakage current increases of 93%, 9336%, and 5677% for chips #1, #2, and #3, respectively. All ring oscillator frequency variations remained below 0.5%, confirming the negligible Total Ionizing Dose (TID) impact on threshold voltage.

Following cryogenic irradiation, an increase of 37 units in the BGR's temperature code was observed for chip #2, which is considerably higher compared to the 15-unit increase noted for chip #1 after room-temperature irradiation. Both leakage current and temperature codes demonstrated a clear cryogenic-temperature-enhanced damage effect. By analyzing the role of temperature on each stage of the TID effect, we found that cryogenic temperatures primarily impact two processes: hole transport and interface trap formation. The underlying mechanism involves significantly reduced hole mobility and suppressed interface trap formation at cryogenic temperatures, resulting in a substantially larger net positive charge accumulation in the Shallow Trench Isolation (STI) compared to that at room temperature. Three-dimensional Technology Computer-Aided Design (TCAD) modeling and simulation confirmed that under 110 K, the inversion layer area at the channel bottom was larger and the electron density was higher than at 290 K. These findings provide important insights for the design and research of FinFET integrated circuits for aerospace applications.

Keywords: Total Ionizing Dose, Cryogenic, FinFET, Leakage Current

INTRODUCTION

FinFET technology, which leverages its tri-gate structure that wraps around the channel on three sides, demonstrates significant advantages over planar devices in terms of suppressing short-channel effects, enhancing carrier mobility, and improving circuit integration density [1]. Consequently, it has become a core component of aerospace electronic systems. However, in missions such as deep-space exploration, devices must endure the synergistic effects of extreme temperatures (e.g., as low as 120 K during Martian nights) and space radiation [2–5]. The unique three-dimensional (3D) architecture and relatively compact construction of FinFETs significantly increase the complexity of their radiation responses. Simultaneously, cryogenic environments profoundly impact key operating parameters of Metal-Oxide-Semiconductor (MOS) transistors, such as threshold voltage, subthreshold leakage current, and subthreshold swing [6, 7], thereby presenting greater challenges for mechanistic analysis of Total Ionizing Dose (TID) effects at cryogenic temperatures. Therefore, understanding the combined impact of high-dose radiation and cryogenic temperatures on spacecraft electronics and implementing corresponding radiation-hardening designs is crucial for ensuring adequate design margins [8, 9].

Research on TID effects in bulk silicon FinFETs at room temperature is relatively mature [10–17]. Existing studies indicate that owing to their ultra-thin gate oxides, the impact of TID on the threshold voltage is generally negligible; instead, the accumulated trapped charge within the Shallow Trench Isolation (STI) oxide is the primary cause of increased leakage current [10, 12]. Wang et al. utilized 3D Technology Computer-Aided Design (TCAD) simulations to investigate the impact of Punch-Through Stop (PTS) doping and fin angle on the TID response of 14 nm bulk silicon FinFETs [13]. Their study revealed that increasing the concentration and depth of PTS doping effectively reduces off-state leakage current induced by TID radiation. However, fin angle demonstrated limited influence on TID susceptibility. Chatterjee et al. examined the relationship between leakage current and radiation dose in triple-well FinFETs under different radiation bias configurations [14]. They observed that leakage current and trapped charge within the STI were most pronounced under off-state bias conditions (drain biased at supply voltage, with gate, source, and substrate grounded) due to the maximized electric field near the STI oxide corners along the bottom of the channel in this state. By comparing the TID response of FinFETs with different numbers of fins (Nfin), Wei et al. found that only single-fin n-type FinFETs (n-FinFETs) exhibited significant radiation damage, while multi-fin devices showed minimal degradation [15]. TCAD simulations revealed that the relative position between the fin and the STI structure decisively influences the TID response of n-FinFETs.

Current research on the TID effects in bulk silicon FinFET devices under cryogenic temperatures remains relatively limited. A study by Ryan Kelle found that when devices with a narrow channel width (15 nm) were irradiated at 90 K, their leakage current increase was significantly higher than that of wider-channel (40 nm) devices—consistent with the narrow-width effect trend observed during room temperature radiation [18]. Conversely, research by the T.D. Haeffner group indicated that under 90 K radiation, devices with wider channels exhibited a more significant leakage current change [19]. Notably, the experimental samples in both studies originated from IMEC, with highly similar device structures and process descriptions, yet their findings were contradictory. This discrepancy underscores the high complexity of the underlying mechanisms governing cryogenic TID effects and emphasizes the necessity of dedicated research on FinFET TID behavior at cryogenic temperatures.

While characterizing the TID response of individual transistors offers the most direct insight into the physical mechanisms of parameter degradation, fabricating and testing dedicated FinFET test chips presents significant challenges. During the manufacturing of single-transistor test chips, plasma etching induces charge accumulation. The sub-femtofarad gate capacitance struggles to dissipate this charge effectively. Although employing transistor parallel arrays can enhance charge dissipation capability, measurement results become susceptible to anomalies from individual defective devices, leading to skewed data. Furthermore, single-transistor structures are highly sensitive to Electrostatic Discharge (ESD), posing a substantial risk of gate oxide breakdown or source-drain punch-through. As indicated in references [18, 19], devices with channel lengths extending to 1000 nm were chosen to prevent source-drain punch-through. This scale is uncommon for FinFET logic circuits. Moreover, varying conclusions from devices of identical size tested under identical conditions underscore the significant sensitivity to measurement fluctuations in the characterization of individual devices.

In contrast, assessing TID effects at the circuit level offers greater practicality [20–22]. Ring oscillator (RO) provides a convenient means to measure radiation-induced changes in logic gate delay and power consumption, directly reflecting variations in transistor drive current. The RO approach aggregates variations in individual transistor parameters into a measurable frequency shift, relying on averaging that inherently mitigates the impact of outlier devices. Additionally, RO data is readily incorporated into ASIC design flows, supporting evaluation of large-scale circuits using advanced simulation tools, and facilitates the development of circuit level TID hardening techniques. Furthermore, despite being a core component in CMOS analog and mixed-signal integrated circuits (ICs), the cryogenic TID response of Bipolar Junction Transistors (BJTs) is scarcely reported. In this work, we present a custom design leveraging a sub-20 nm bulk silicon FinFET process to implement ring oscillators (ROs) that incorporate transistors with different threshold voltages. We monitor variations in supply current and oscillation frequency to observe device performance degradation after radiation at different temperatures. Simultaneously, we incorporate bandgap reference (BGR) circuits to enable observation of BJT performance variations under radiation across the same temperature range.

MATERIAL AND METHODS

Based on a sub-20 nm bulk silicon FinFET process, we fabricated custom test chips and packaged using flip-chip technology. The test circuits primarily consist of ring oscillators formed with standard threshold voltage (SVT), low threshold voltage (LVT), and ultra-low threshold voltage (ULVT) transistors, respectively, alongside a BJT-based bandgap reference circuit. Each RO comprises 80 inverter stages and one NAND gate, with the NAND gate enabling/disabling the oscillation. Within the RO inverters, the n-FinFETs and p-FinFETs share identical dimensions.

To achieve the cryogenic conditions, a customized extreme temperature test system, specifically designed for radiation environments, was employed. The system can achieve a minimum vacuum level of 0.1 Pa and offers a theoretical controlled temperature range from 80 K to 500 K. To ensure temperature stability and measurement accuracy, test temperatures of 110 K and 290 K were selected. The TID radiation experiments were performed using a ⁶⁰Co γ-ray source at Xinjiang Technical Institute of Physics and Chemistry. A dose rate of 200 rad(Si)/s was used to achieve a total dose of 1 Mrad(Si). The core voltage and I/O voltage were maintained at 0.8 V and 1.8 V, respectively. In-situ measurements were performed every 250 krad(Si) dose increment, followed by post-irradiation annealing measurements at room temperature (290 K).

Given that conventional power supplies lack sufficient current measurement resolution to accurately characterize sub-microampere leakage currents at cryogenic temperatures, this study employs a high-precision Source Measure Unit (SMU) system (Keithley 2636B) for integrated power supply and measurement. The instrument dynamically optimizes the signal-to-noise ratio through real-time auto-ranging technology, achieving a resolution of 100 fA in its minimum range (100 nA). Combined with electrostatic shielding and low-noise cabling configurations, the system achieves a total measurement uncertainty of 0.5%. This approach successfully resolved leakage current differences as low as 1 nA between chip #1 and chip #2 at 110 K, providing foundational assurance for quantifying cryogenic radiation damage.

A total of three chips were subjected to radiation testing. Chips #1 and #2 were irradiated at 290 K and 110 K, respectively. Motivated by the more pronounced leakage current variation observed at 110 K, chip #3 was added for comparative validation under identical cryogenic conditions. For the 110 K condition, after completing in-situ measurements at 1 Mrad(Si), the temperature was raised to 290 K, and in-situ measurements were performed at three temperature points of 170 K, 230 K, and 290 K, respectively. For the 290 K condition, after completing in-situ measurements at 1 Mrad(Si), the temperature was lowered to 110 K for measurement, then raised to 290 K, and in-situ measurements were performed at three temperature points of 170 K, 230 K, and 290 K, respectively.

RESULTS AND DISCUSSION

A. Leakage Current

The total ionizing dose response characteristics of bulk silicon FinFET devices are primarily dominated by the trapping of radiation-induced positive charge within the shallow trench isolation oxide [10, 11, 14]. As the accumulated radiation dose increases, the build-up of trapped charge in the STI can form source-to-drain leakage paths via the "subfin" region of the bulk silicon FinFET structure [23, 24]. Fig. 1(a) presents the progression of leakage current in the core voltage domain for chip #1, which was subjected to radiation at 290 K, as well as chips #2 and #3, which underwent radiation at 110 K, all plotted against varying radiation doses. The leakage current of chip #1 tends to saturate after reaching 500 krad(Si), whereas the leakage currents of chips #2 and #3 exhibit exponential growth with accumulating dose. After 1 Mrad(Si) irradiation, chip #1 shows a 113% increase compared to its pre-irradiation value; chip #2 shows a 7133% increase and chip #3 shows a 4248% increase relative to their pre-irradiation baselines. It should be noted that chip #1 was irradiated at 290 K, and its leakage current was slightly higher than that of chips #2 and #3 at a radiation dose of 250 krad(Si).

Fig. 1(a) also shows the leakage current measured for chip #2 immediately after completing the 1 Mrad(Si) radiation dose, while maintaining the temperature at 110 K and under constant bias. Measurements were taken every 5 minutes over a total duration of 1 hour. The results demonstrate that the leakage current decreased exponentially over time under these conditions. Chip #3 exhibited a similar trend when tested under the same protocol.

Fig. 1(b) and Fig. 1(c) plot the leakage current versus temperature for each chip before and after radiation, respectively. Comparison reveals that chips #2 and #3 exhibit a more pronounced increase in leakage current with rising temperature after radiation. At 290 K, chips #1, #2, and #3 exhibit increases of 93%, 9336%, and 5677% respectively, compared to their pre-irradiation values.

Modern digital circuits typically implement logic functions using complementary pairs: pull-up PMOS and pull-down NMOS transistors. Since these transistors employ different types of charge carriers for conduction in their channels when turned on, their responses to total ionizing dose effects differ significantly. As elaborated in reference [25], no leakage current degradation was observed in any PMOS samples. This absence stems from the fundamental reason that positive trapped charge within the isolation regions cannot form a parasitic hole leakage current path within the n-type doped "subfin" region. Consequently, this study focuses exclusively on investigating the leakage current degradation mechanism in NMOS devices.

To elucidate the physical mechanisms underlying the temperature-dependent differences in TID response, 3D modeling and simulation were performed using the Sentaurus TCAD tool [26, 27]. The device structure was constructed based on a typical FinFET process flow. Key geometric and process parameters were obtained from the foundry-provided Process Design Kit (PDK), with a subset listed in Table 1.

TABLE 1. Key parameters of n-FinFET TCAD model

The FinFET structure exhibits mirror symmetry along the channel direction relative to its centerline. Consequently, simulating only half of the device structure yields identical internal distributions of electrical quantities (e.g., potential, electric field, carrier concentration) as simulating the full structure. This symmetry principle was exploited to significantly speed up simulations. The simulated half-structure is illustrated in Fig. 2(a).

Model calibration involved simulating ID-VG curves using Sentaurus Device and comparing them with SPICE simulation results. After defining device structure and doping parameters, adjusting parameters in physical models ensures consistency between TCAD and SPICE simulation results, significantly enhancing simulation accuracy and reliability. The models primarily include: philips unified mobility, high-field mobility saturation, inversion and accumulation layer mobility (IALMob), thin-layer mobility, high-k degradation mobility, density-gradient quantum correction with auto-orientation, stress effects, band-to-band tunneling leakage current and Shockley–Read–Hall (SRH) model, auger for recombination. It is noteworthy that incomplete ionization model and temperature-dependent band gaps must be considered for accurate cryogenic simulations. Fig. 2(b) compares the simulated transfer characteristics of the device with SPICE simulation results. As shown, the TCAD simulation curve exhibits close alignment with the SPICE simulation data, indicating highly consistent agreement between the device's electrical behavior simulation and SPICE modeling outcomes.

Reference [28] proposed a TCAD-based radiation simulation approach that effectively characterizes device total ionizing dose effects. Within this model, the density of electron-hole pairs (ehp) surviving initial recombination in the STI after γ-ray radiation can be expressed as,

$$G_r = g_0 \cdot D \cdot Y(E)$$

$$Y(E) = \left(\frac{E + E_0}{E + E_1}\right)^m$$

Where $g_0 = 7.6 \times 10^{12}$ ehp·rad⁻¹·cm⁻³ represents the number of electron-hole pairs generated per unit volume in SiO₂ per rad of absorbed radiation energy. $D$ is the accumulated radiation dose. $Y(E)$ is the electric-field-modulated hole yield function. $E_0 = 0.1$ V/cm and $E_1 = 1.35 \times 10^6$ V/cm are field-dependent correction parameters. $m = 0.9$ is an exponential correction factor. During radiation simulation, the device was biased in the ON state, gate voltage $V_G = 0.8$ V, with all other terminals grounded. Post-irradiation characterization involved applying a fixed drain-source voltage of 0.05 V while sweeping the gate voltage up to 0.8 V.

As shown in Fig. 3(a), the device's ID-VG characteristics exhibited negligible change after radiation at 290 K. Fig. 3(b) demonstrates that leakage current increased dramatically with accumulating radiation dose at 110 K. Fig. 3(a) and Fig. 3(b) also show cross-sectional views along the fin width direction for devices irradiated to 1 Mrad(Si) at 290 K and 110 K, respectively. Comparison reveals that under cryogenic radiation (110 K), the inversion layer area near the channel bottom interface is significantly larger. The electron concentration within this inversion layer is substantially higher.

The total ionizing dose effects typically involve five key physical processes: (1) initial recombination following electron-hole pair generation induced by radiation; (2) hole transport via drift within the oxide; (3) capture by deep-level hole traps; (4) generation of interface traps; and (5) annealing of partially captured charges. The following section will provide a detailed examination of these fundamental processes, with particular focus on how temperature affects each stage.

Initial Recombination: Given a specific incident particle type and material system, the number of electron-hole pairs that escape initial recombination is primarily governed by the ambient temperature and the applied external electric field. Due to the significant separation between nascent electron-hole pairs, interactions between different pairs can reasonably be neglected. In other words, each pair, coupled by their mutual coulombic attraction, undergoes counter-directional drift driven by the local electric field, simultaneously accompanied by random diffusive motion due to thermal excitation within the system. Ausman implemented numerical simulations of the recombination kinetics for isolated electron-hole pairs under an applied electric field, based on the Onsager solution to the Smoluchowski equation, and conducted comparative analyses at 20°C, -80°C, and -193°C [29]. The modeling results indicate that, except under very low electric field conditions, this recombination process is generally unaffected by temperature variations. Conversely, the escape probability of electron-hole pairs increases significantly with rising electric field strength.

It is noteworthy that within the STI region, the initial fringing electric field originates primarily from the longitudinal component induced by the gate structure. However, subsequently radiation-induced trapped charges establish a built-in electric field perpendicular to the SiO₂-Si interface. We infer that radiation-induced trapped charges during radiation continuously modify the local electric field distribution, thus dynamically affecting the escape probability of electron-hole pairs. Consequently, the hole yield does not remain constant but exhibits a gradually increasing trend with accumulating radiation dose.

Hole Transport: Within shallow trench isolation structures, at room temperature, the electron mobility is approximately 20 cm²·V⁻¹·s⁻¹, while the hole mobility is around 1 × 10⁻⁴ cm²·V⁻¹·s⁻¹, roughly 5 orders of magnitude lower [28]. Owing to this stark disparity in carrier mobility, electrons that escape initial recombination can be rapidly extracted from the STI region on a sub-picosecond timescale. Concurrently, a significant number of holes that fail to recombine with electrons are captured by oxide defects, forming equivalent positive charge centers (or an equivalent positively charged oxide layer) within the oxide. The "subfin" region affected by this equivalent positive charge layer forms a parasitic electron leakage path. According to findings in reference [30], the electron mobility within the STI oxide layer increases as temperature decreases; conversely, the hole mobility decreases significantly. When the temperature drops from 290 K to 110 K, the hole mobility decreases by over 10 orders of magnitude. Current analysis suggests that the predominant transport mechanism for holes is likely polaronic hopping between localized shallow trap states. The concept of a "polaron" refers to a phenomenon where a charge carrier (here, a hole) interacts strongly with the surrounding medium, causing lattice distortion in its immediate vicinity—a state also known as self-trapping. Consequently, when a hole migrates through the material, it effectively moves accompanied by the lattice distortion it induces. The strongest experimental evidence supporting the polaron hopping mechanism is the observation that hole transport exhibits thermally activated behavior above approximately 140 K, transitioning to non-activated behavior at lower temperatures—a hallmark signature of polaronic transport [31].

Deep Hole Trap Capture: These defects are typically located near the SiO₂-Si interface but can also extend into the bulk region. The formation of deep-level hole traps near the SiO₂-Si interface is primarily associated with a transition region resulting from incomplete oxidation. This transition region contains non-ideal structures such as dangling silicon bonds and oxygen vacancies. A typical defect structure involves the absence of an oxygen atom in the lattice, leading to the formation of a weak Si-Si bond; in this configuration, the relevant silicon atom is coordinated with only three surrounding oxygen atoms. When a trap captures a positive charge, it can cause the Si-Si bond to break, accompanied by lattice relaxation. As research progresses, scholars increasingly recognize the dynamic response characteristics and importance of these traps located near the interface that can exchange charge with the underlying silicon substrate over broad timescales [32]. Although physically located within the oxide, these defects can exchange charge with silicon via electron tunneling. During interface state measurement using charge pumping techniques, they become coupled into the measurement, leading to their misidentification as part of the interface traps. It has been proposed to term these defects "boundary traps."

Interface Trap Generation: Radiation-induced interface trap formation can occur relatively shortly after radiation or through a long-term, slow process. Research by Saks et al. revealed a significant temperature dependence in the generation mechanism of interface traps [33]. At near-room temperature, the primary formation pathway involves: a hole captured in a deep-level trap reacting with a mobile neutral hydrogen atom (H⁰) within the silicon dioxide, generating a hydrogen ion (H⁺); this H⁺ then drifts under the influence of the electric field to the SiO₂-Si interface, where it reacts with an Si-H bond on an interface dangling bond, breaking the Si-H bond and thereby creating an interface state. In cryogenic environments, however, the drift motion of H⁺ is "frozen" due to thermodynamic limitations. Under these conditions, the dominant mechanism for interface trap formation shifts from proton drift to diffusion of neutral hydrogen atoms. Experimental observations indicate that the density of interface states generated via the H⁰ diffusion mechanism at cryogenic temperatures is at least an order of magnitude lower compared to the room-temperature pathway.

Annealing: This process follows a logarithmic time dependence. Although holes trapped within the oxide are in a metastable state, they indeed undergo a continuous annealing process that can span timescales from hours to years, exhibiting significant coupled dependence on time, temperature, and applied electric field. Typically, the annealing of trapped holes occurs via two competing mechanisms: quantum mechanical tunneling or thermally stimulated release. At or near room temperature, tunneling is the dominant mechanism; when the temperature rises above a critical threshold, the thermally stimulated process gradually becomes dominant [31].

As analyzed previously, during the initial recombination stage, the drastic decrease in hole mobility at 110 K (approximately 10 orders of magnitude lower than at room temperature) results in a significantly larger increase in the electric field component perpendicular to the interface compared to room temperature conditions. This, in turn, leads to a systematic enhancement of the hole yield during low-temperature radiation, exhibiting a monotonically increasing trend with accumulating dose.

During the hole transport stage, the dual constraints of suppressed H⁺ migration due to cryogenic "freezing" and extremely low hole mobility at 110 K cause substantial accumulation of positive charge within the STI structure. This accumulation subsequently leads to a carrier concentration in the parasitic transistor channel far exceeding that under room temperature conditions. Regarding interface trap behavior, at 110 K, the electric-field-driven drift of H⁺ is essentially halted due to thermodynamic barriers, leaving only the H⁰ diffusion mechanism active. However, the interface state density generated by this mechanism is at least an order of magnitude lower than at room temperature and can be neglected.

Collectively, these low-temperature characteristics result in a significant enhanced radiation-induced degradation of leakage current at 110 K.

Concerning the subsequent behavior of deep-level hole traps, the near-interface portion of the hole charge trapped within the oxide will form boundary traps. Given the weak temperature dependence of the quantum tunneling process, electrons can tunnel to these boundary traps with relatively high probability to achieve charge compensation. This mechanism explains the approximately 33% rapid annealing observed within one hour post-irradiation at 110 K.

The sharp increase in leakage current observed during post-irradiation warming can be attributed to the temperature-dependent reduction in the threshold voltage of parasitic transistors. Upon reaching room temperature (290 K), the leakage currents of chips #2 and #3 were 49 times and 31 times higher, respectively, than that of chip #1 irradiated at room temperature. This substantial disparity further corroborates that the density of fixed charges trapped within the STI oxide is significantly higher following cryogenic radiation compared to room-temperature radiation.

Notably, under identical 110 K cryogenic radiation conditions, chips #2 and #3 exhibit significant dispersion in leakage current degradation. The leakage current of chip #2 is 1.64 times higher than that of chip #3 after 1 Mrad(Si) irradiation. Ring oscillator frequency measurements further reveal that the oscillation frequency of chip #3's RVT RO is approximately 2.4% higher than that of chip #2. This phenomenon suggests that inherent process variations may modulate total ionizing dose effects in extreme environments, as reported at room-temperature conditions in reference [34]. Subsequent studies will conduct systematic cryogenic radiation experiments on multi-corner test chips to establish a quantitative correlation model between process deviations and cryogenic radiation damage. This will provide critical guidance for process selection in deep-space applications.

B. Ring Oscillators

Ring Oscillators play a critical role in radiation effects research and mechanism studies, particularly within semiconductor devices, aerospace electronics, and nuclear technology [35]. Their core value lies in revealing radiation damage mechanisms in materials and device failure modes through monitoring changes in parameters such as oscillation frequency and power consumption [36]. Threshold voltage shifts and carrier mobility degradation can affect device drive current, leading to significant changes in ring oscillator output frequency. As shown in Fig. 4, the RO frequency demonstrates negligible variation with increasing radiation dose for both chip #1, chips #2 and #3. Across all tested devices, the maximum frequency shift was observed in chip #3's RVT ring oscillator, amounting to a mere 0.5%. This aligns with findings in reference [35], where 7 nm FinFET devices irradiated at room temperature to 435 krad(SiO₂) exhibited no more than 1% variation in RO frequency.

This stability can be attributed to two key factors. First, in FinFET technology, the ultra-thin gate oxide thickness renders the impact of total ionizing dose effects on threshold voltage negligible [35]. Second, the leakage current increase induced by TID effects remains negligible compared to the ON-state current.

Chip #1 was irradiated at room temperature. Due to the inverse temperature dependence of RVT and LVT transistors, its ring oscillator frequency is higher than that of chip #2. Chip #2 and chip #3 underwent identical testing conditions, differing only in the process corner during fabrication. Comprehensive comparison reveals that the ring oscillator frequency variation caused by process deviations is comparable in magnitude to that induced by the 180 K temperature difference.

C. Bipolar Junction Transistor

The Bipolar Junction Transistor serves as a core component in CMOS analog and mixed-signal integrated circuits. By appropriately combining the negative temperature coefficient of a BJT's base-emitter voltage with the positive temperature coefficient derived from the difference in base-emitter voltages between two identical BJTs operating at unequal current densities, it is possible to generate a reference voltage that is substantially independent of temperature. Compared to pure CMOS implementations, BJT-based bandgap references offer superior accuracy and significantly lower temperature drift.

Given that CMOS processes are fundamentally optimized for MOSFETs, BJTs are typically integrated onto the same chip through specialized design. Vertical PNP transistors are implemented using the inherent structure of PMOS devices, P⁺ active region (Emitter) / N-well (Base) / P-substrate (Collector). Vertical NPN transistors utilize the NMOS structure, N⁺ active region (Emitter) / P-well (Base) / Deep N-well (Collector). Implementing NPN transistors requires an additional deep N-well masking layer compared to PNP transistors. Consequently, bandgap reference circuits in CMOS technologies predominantly employ PNP BJTs for enhanced design efficiency and cost-effectiveness.

The bandgap reference circuit implemented in this work, based on PNP transistors, is shown in Fig. 5(a), where R1 = R2 and maintains Vₓ = Vᵧ through virtual short principle. The output V_BG provides a temperature-independent reference voltage, serving as the stable bias for subsequent voltage readout circuits. As temperature increases, the emitter-base voltage Vᵧ of transistor Q₀ decreases while its collector current rises. Consequently, the voltage drop across resistor R₁ is amplified and digitized to monitor on-chip temperature variations. This digitized output is designated as the Temperature Code (TC). Experimental characterization demonstrates a linear response where TC increases by 1.94 per 1 K temperature rise across the 110 K to 290 K operational range.

As shown in Fig. 6, all three chips exhibit distinct differences in leakage current values across different supply voltages, with leakage current increasing proportionally at higher voltages. However, the TC remains remarkably consistent across different supply voltages at the same accumulated radiation dose, with variations confined to no more than 2 units, while it demonstrates a cumulative increase with rising total radiation dose. After 1 Mrad(Si) irradiation, the temperature code shows cumulative increases of 37 units for chip #2, 30 units for chip #3, and 15 units for chip #1, with the increases for chips #2 and #3 being significantly larger than that for chip #1. Chip #1 was irradiated at room temperature without active temperature control. During radiation, its temperature exhibited a gradual upward drift, with recorded temperatures of 290 K, 291 K, 292 K, 293 K, and 293 K at different radiation dose points. The temperature rise contributed approximately 6 units to the temperature code increase, while the genuine total ionizing dose effects accounted for 9 units of the increase. This temperature rise can be attributed to two factors, gamma-ray heating (energy deposition from incident radiation) and the self-heating effect inherent to FinFET technology. Chips #2 and #3 were maintained at a strictly controlled constant temperature throughout radiation, and their TC increases were consistent across different supply voltages. This conclusively rules out any significant contribution from NMOS leakage current elevation induced by TID effects.

In the context of bulk silicon CMOS technology, vertical PNP bipolar transistors are constructed using a layered structure, consisting of a P⁺ active region (Emitter), an N-well (Base), and a P-substrate (Collector), as illustrated in Fig. 5(b). Following radiation, holes generated within the shallow trench isolation oxide adjacent to the "subfin" region become predominantly trapped near the SiO₂-Si interface. Based on the prior analysis of temperature sensitivity for the five key TID effect processes, although current gain degradation manifests as increased base recombination current at both 290 K and 110 K, their underlying mechanisms differ fundamentally. At 290 K, the rise in recombination current is primarily driven by interface traps; at 110 K, the recombination enhancement is dominated by boundary traps. This radiation-induced leakage current significantly elevates the base current component, thereby causing degradation of the current gain [37, 38]. When such irradiated bipolar transistors are integrated into Proportional-to-Absolute-Temperature (PTAT) sensors, their output voltage exhibits substantial drift, directly compromising sensor accuracy.

Analysis of the circuit shown in Fig. 5(a) explains this phenomenon. When all transistors exhibit identical, small radiation-induced base leakage currents (ΔI_B), the Q₁ branch (with 8 transistors) accumulates 8 times more ΔI_B than the Q₀ branch (with 1 transistor). Due to operational amplifier A₁ enforcing Vₓ = Vᵧ, currents through both branches remain equal. Given this significant imbalance in radiation-induced current, Vᵧ increases to raise Q₀'s emitter current, ensuring branch current equality. Since the DC resistance of Q₀'s forward-biased emitter-base junction is significantly smaller than R₁, the increase in voltage drop across R₁ is much larger than the increase in Vᵧ. This ultimately causes the output temperature code to increase significantly.

CONCLUSION

Through comparative studies of total ionizing dose effects in sub-20 nm bulk silicon FinFET technology across different temperatures, we observed that ring oscillator frequencies exhibit negligible variation under both room-temperature (290 K) and cryogenic (110 K) radiation, with a maximum frequency deviation of merely 0.5%. This indicates that TID-induced threshold voltage shifts in CMOS transistors are insignificant. However, cryogenic radiation significantly amplifies leakage current through TID-induced STI parasitic electron leakage path, demonstrating a pronounced cryogenic radiation damage enhancement effect. Analyzing temperature-dependent TID mechanisms reveals that cryogenic conditions primarily impact two processes: hole transport and interface trap formation. The underlying mechanisms are a drastic reduction in hole mobility and suppressed interface trap generation at cryogenic temperatures, collectively leading to a significantly higher density of net positive charge within STI oxides compared to room temperature. TCAD modeling and simulations confirm that at 110 K, the inversion layer area near the channel bottom interface is larger and the electron concentration is substantially higher than at 290 K.

BJTs also exhibit enhanced cryogenic damage effects post-irradiation. Although current gain degradation manifests as increased base recombination current at both 290 K and 110 K, increased interface trap density dominates the recombination process at 290 K, consistent with the classical model of Si-H bond dissociation via hydrogen ion drift; at 110 K, boundary traps become the primary cause of current gain degradation through tunneling-assisted recombination mechanisms. These findings provide critical insights for the design and research of radiation-hardened FinFET integrated circuits in aerospace applications.

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