Preamble

Development of an Innovative Real-Time Dosimetry Monitoring System for Heavy Ion Radiotherapy

Lingling Liu,¹,² Qianshun She,¹,²,† Jie Kong,¹,² Junwei Yan,¹,² Zhiguo Xu,¹,² and Yuhan Dou¹,²
¹Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China
²University of Chinese Academy of Sciences, Beijing 100049, China

Cancer is the second leading cause of mortality globally. As a critical technological approach in oncology treatment, radiation therapy includes conventional dose rate radiation therapy, high dose rate radiotherapy, and ultra-high dose rate radiotherapy (FLASH-RT). With the significant escalation in radiotherapy dose rates, real-time dosimetry monitoring faces the dual challenges of enhancing both response time and measurement precision. This work successfully developed a real-time dosimetry monitoring system for radiotherapy, designed to accommodate a broad range of dose rates. The system consists of a dual-gated integrator architecture front-end circuit and a high-speed data acquisition circuit, providing accurate detection of bipolar current pulse signals spanning from -190 µA to +200 µA, with a minimum current measurement range from -1 pA to 1 pA. Two significant technological advancements were accomplished: first, the elimination of signal processing dead time resulted in a reduction of the single-event readout time to 5 µs; second, the nonlinear error from -190 µA up to the maximum current is within 0.67%, with a linear correlation coefficient (R²) of 0.99992. The experiments were conducted using an ionization chamber detector at the Heavy Ion Research Facility in Lanzhou (HIRFL-TR4). This system, combined with a dose detector, achieves real-time dose measurement within the dose rate range of 65 Gy/min to 120 Gy/min. It demonstrates excellent real-time monitoring performance in the high-dose rate range of radiation therapy and shows potential for further application in dose monitoring for electron and proton beam radiotherapy.

Keywords: Real-time dosimetry monitoring, Heavy Ion Radiotherapy, Data acquisition circuit, Analog front-end circuit

INTRODUCTION

Malignant tumors represent a significant threat to human health, with radiation therapy being one of the most crucial treatment methods for cancer. Unlike traditional photon radiation, heavy ion beams exhibit a Bragg peak—a concentrated dose deposition whose depth can be finely adjusted by altering the beam energy \cite{1}. This feature enhances protection for healthy tissues \cite{2}. As such, it is currently regarded as the most optimal form of radiation therapy in clinical practice \cite{3,4}. Ion therapy includes conventional dose rate radiotherapy, high dose rate radiotherapy, and ultra-high dose rate radiotherapy known as FLASH-RT \cite{5–9}. Research indicates that high-dose per fraction radiotherapy can suppress tumor-reactive immunity \cite{10}, while ultra-high dose rate radiotherapy (FLASH-RT) notably reduces the toxicity of radiation to normal cells surrounding tumor cells \cite{11–17}. The effectiveness and quality of ion beam therapy are strongly correlated with the dose of the beam delivered to the patient. Consequently, beam monitoring is essential for ensuring the precision and efficacy of ion therapy \cite{18}. Typically, ionization chambers are used as dose detectors at the end of heavy ion radiotherapy to measure the dose \cite{19–26}. The current signal produced by the ionization chamber is directly proportional to the dose delivered during beam radiation therapy. The characteristics of dose ionization chamber detectors are that they can neglect dependence on the particle energy and linear energy transfer, while exhibiting high reproducibility and accuracy. As a result, ionization chambers are regarded as the gold standard for monitoring radiation therapy doses \cite{27,28}.

The shallow-layer treatment and biological irradiation terminal at the Lanzhou Heavy Ion Research Facility (HIRFL) is capable of conducting mutagenic breeding and heavy-ion cancer treatment research using different ion species, energies, and dose rates. The layout of the beam monitoring system detectors for this terminal is shown in Fig. 1 [FIGURE:1].

Fig. 1. Layout of the beam monitoring system detectors for terminal.

The dose measurement for the terminal uses a flat-type ionization chamber, as shown in Fig. 2 [FIGURE:2]. It consists of four parts: a metal-sealed housing, an entrance window, an exit window, an electrode core, and an insulating base. The electrode core uses a three-layer electrode, with a central anode and cathodes at both ends, all made from a 13 µm double-sided aluminum-coated polyimide film. The aluminum coating thickness is 100 nm. Both the entrance and exit windows are made from 25 µm thick double-sided aluminum-coated polyimide film. The overall equivalent water thickness is less than 0.1 mm.

To eliminate the effects of air humidity and atmospheric pressure on charge collection efficiency, high-purity nitrogen gas at a fixed pressure is used as the working gas. The ionization chamber operates at a negative high voltage to collect electrons, and the current (charge) signal generated is directly output and read by a new-type real-time dose monitoring system. The beam energy for the shallow-layer heavy-ion cancer treatment terminal is 80–100 MeV/u (¹²C⁶⁺). At atmospheric pressure, the charge signal output by the flat-type ionization chamber can reach a maximum of 10 µA. The terminal is currently conducting research on high and ultra-high dose rate heavy-ion cancer treatment. As the dose rate increases, the demands for real-time dose monitoring in terms of difficulty, importance, and accuracy are progressively heightened. This places the following requirements on the electronics: the detectable current signal should reach at least 10 µA (having redundancy is preferred), the front-end circuit should have minimal dead time, the processing time for a single event should be less than 10 µs, and the integral nonlinearity (INL) is required to be less than 1% over the entire dynamic range.

Columns 2 and 3 of Table 1 present the range of current output from the ionization chamber for various radiation therapy devices at corresponding dose rate conditions. The output signal from the dose ionization chamber detector varies due to differences in beam intensity and the chamber's actual gain. Therefore, the dose monitoring readout electronics must be capable of measuring input signals in the range of pA to µA \cite{29}.

Columns 4 and 5 of Table 1 present the readout electronics system for dose ionization chambers and their linearity relationship for different radiation therapy devices. As shown in the table, internationally, the measurement of current signals output by dose detection ionization chambers generally uses Very Large Scale Integration (VLSI) \cite{35}, Application-Specific Integrated Circuits (ASICs) \cite{36}, or discrete components \cite{37–39}. VLSI and ASIC devices are characterized by high integration, low power consumption, and exceptional stability; however, their development is complex, with long timelines, limited versatility, and slow technological advancements. In contrast, measurement circuits based on discrete components provide greater flexibility, lower cost, and faster technological updates, but they tend to occupy more circuit board space, have lower integration, and are more susceptible to noise interference.

Two commonly used readout schemes utilizing discrete components are as follows. The first scheme uses an integrator circuit combined with an Analog to Digital Converter (ADC) for sampling and output \cite{22}. This approach directly integrates the current to obtain the charge, making it relatively simple and insensitive to AC noise. The measurement range can be adjusted by selecting an appropriate capacitance based on the beam intensity. The second scheme converts the current into a voltage, which is subsequently converted into a frequency output \cite{40}, with the charge measured via a count. This scheme is conducive to digital processing and provides high accuracy. Nevertheless, its linear range is limited, and when the current approaches the measurement threshold, the linearity may deviate, leading to measurement errors. As such, this approach is not suitable for general-purpose designs.

In order to facilitate dose measurements that are compatible with both high dose rate and conventional dose rate radiotherapy, specifically covering current outputs ranging from hundreds of pA to hundreds of µA as typically provided by ionization chambers, we have developed an innovative real-time dose monitoring readout system. This system utilizes a dual-gated integrator architecture for the analog front-end (AFE) circuit to directly integrate the current. Coupled with a data acquisition (DAQ) circuit for sampling and readout, the system is capable of covering a wide bipolar dynamic current range of -190 µA to 210 µA, thus meeting the readout requirements of the majority of ionization chamber detectors used in particle therapy dose measurements.

In conventional designs, current signals are acquired after passing through the AFE circuit. During the acquisition period, the AFE circuit must maintain the current voltage, rendering it incapable of responding to real-time input currents, thereby causing dead time. This dead time limits the detector's ability to record all events, potentially compromising the completeness of data acquisition and subsequently affecting the precision and efficacy of the treatment process. Furthermore, the response capability to high-frequency events, which is directly related to the processing time of individual events, can impact the accuracy of real-time monitoring. To address these limitations, the proposed real-time dose monitoring readout system utilizes a dual-gated integrator architecture in the analog front-end processing circuit. By enabling two integrators to operate alternately, the system effectively eliminates dead time and reduces the individual event processing time to 5 µs.

II. SYSTEM STRUCTURE

The schematic diagram of the innovative real-time dosimetry monitoring system development is shown in Fig. 3 [FIGURE:3]. The system consists of two primary components: an innovative analog front-end (AFE) circuit based on a dual-gated integrator architecture, and a data acquisition (DAQ) circuit. The AFE utilizes a dual-gated integrator to segment and process the weak current signals from the detector, converting them into voltage. This voltage signal is subsequently sampled and encoded by a pipeline-style analog-to-digital converter (ADC). The Field Programmable Gate Array (FPGA) on the DAQ circuit board is responsible for synchronizing and compressing the encoded data. Additionally, the FPGA logic control circuit manages the conversion process of the AFE circuit, ADC sampling, and other associated operations. Finally, the FPGA communicates with the host computer via USB, enabling command transmission and uploading of dose data. The host computer processes the transmitted data and displays it in real time.

Fig. 3. The diagram of readout system.

Fig. 4. AFE circuit.

A. AFE Circuit

As shown in Fig. 4 [FIGURE:4], the AFE circuit consists of dual-gated integrators, a multiplexer, an optocoupler isolator, an attenuation circuit, and a Complex Programmable Logic Device (CPLD). The current signal output from the ionization chamber alternately enters the two gated integrators, is converted into a voltage signal, and then selected and output controlled by the CPLD via the multiplexer. Upon receiving the external trigger signal TrigIn, the circuit is activated. Integrator A begins integrating during the high-level period, generating a voltage signal. Simultaneously, the CPLD controls the multiplexer to output the voltage from Integrator B, which is held for a certain duration to allow digitization by the DAQ circuit. Afterward, the voltage is discharged to complete initialization. When TrigIn transitions, Integrator B starts integrating and generating a voltage, while the CPLD switches the multiplexer to output the voltage from Integrator A. This voltage is similarly held for digitization and then discharged. The image of the AFE circuit is shown in Fig. 5 [FIGURE:5]. As the AFE circuit is located near the beam area, a shielding enclosure is employed to enhance its radiation tolerance, effectively reducing external radiation interference and improving system stability.

Fig. 5. Image of AFE circuit.

1. Dual-Gated Integrator Architecture Circuit

The dual-gated integrator architecture circuit is constructed using two integrators in conjunction with four high-speed switching gates, as shown in Fig. 6 [FIGURE:6].

Fig. 6. Dual-gated integrator architecture circuit.

The dual-gated integrator architecture circuit begins operation after power-on reset. The alternating hardware operation states during its working period are illustrated in Fig. 7 [FIGURE:7].

Fig. 7. Dual-gated integrator architecture circuit alternating hardware operation states.

1. State 1: The input current is integrated by Integrator A, with its integration switch closed and discharge switch open. Integrator B remains with both switches open. The DAQ circuit samples the voltage from Integrator B.
2. State 2: After the voltage sampling from Integrator B is completed, the AFE circuit closes the discharge switch of Integrator B to discharge the voltage. Meanwhile, Integrator A continues integrating.
3. State 3: Upon completion of the discharge, Integrator B begins integration as its integration switch closes. Simultaneously, both switches of Integrator A are opened to halt integration. The DAQ circuit then samples the voltage from Integrator A.
4. State 4: After the DAQ circuit finishes sampling the voltage from Integrator A, the discharge switch of Integrator A is closed, and the AFE circuit discharges the voltage from Integrator A. Once the voltage from Integrator A is fully discharged, the cycle returns to State 1, where the integration and discharge switches of Integrator B are both opened, halting integration in Integrator B, and Integrator A starts the integration process again while the DAQ circuit samples the voltage from Integrator B. This process repeats continuously.

The integration switch is closed only when the discharge switch is open. During the short period that the integration switch is open (approximately 100 ns), any signal current produced by the ionization chamber will charge the ionization chamber's effective input capacitor. This charge is then transferred to the integrating capacitor when the integration switch is closed. As a result, no charge produced by the ionization chamber is lost and the input signal is continuously integrated. Even fast input pulses are accurately integrated.

To eliminate errors caused by baseline drift, the integration output voltage $V_O$ is calculated by subtracting the baseline voltage $V_{baseline}$ from the measured voltage $V$, as defined in Eq. (1):

$$V_O = V - V_{baseline}$$

The functional relationship between the output charge $Q$ of a single integration and the output voltage is given by Eq. (2):

$$Q = C_{INT} V_O = I_{IN} T_{INT}$$

Where $I_{IN}$ is the input current and $C_{INT}$ is the integration capacitor. To ensure the accuracy of the calculated results, the value of $C_{INT}$ should be accurately calibrated in the laboratory to minimize deviations from theoretical values and ensure measurement accuracy.

Assuming the input current is integrated over a certain period, the total accumulated charge is given by Eq. (3):

$$\sum_{i=1}^{N} Q_i$$

Where $Q_i$ is the output charge of the $i$th integration cycle.

Suppose the input current is 100 µA, each integration period is 5 µs, and the integration capacitance is calibrated to 100 pF, the output charge per cycle is calculated as follows in Eq. (4):

$$Q = I_{IN} T_{INT} = 500 \text{ pC}$$

If the input current is continuously integrated over 1 ms, corresponding to 200 events, the total accumulated charge is calculated by Eq. (5):

$$\sum_{i=1}^{200} Q_i = Q_1 + Q_2 + Q_3 + \cdots + Q_{200} = 100 \text{ nC}$$

The output current pulse signal range of the dose ionization chamber detector exhibits a large span. The gated integrator can adjust the gain to accommodate different input ranges. The circuit's conversion gain is determined by both the integration time and the integration capacitance. Specifically, the output voltage is proportional to the integration time and inversely proportional to the integration capacitance. Higher gain can be obtained by increasing the integration time or reducing the integration capacitance. When the input signal is large, the integration time of the gated integrator is shortened, whereas when the input signal is small, the integration time is increased. The gated integrator is highly flexible, capable not only of converting and amplifying current to voltage but also of effectively mitigating noise and interference signals that fluctuate around the baseline by integrating them out, resulting in a significant reduction of noise and interference. Furthermore, the gated integrator used in this circuit features on-chip integrated capacitors, which helps to minimize the impact of leakage voltage caused by dielectric losses in the integration capacitor.

The traditional single integrator architecture typically has a dead time between integration and discharge (a blank period during charge signal processing) which can result in increased measurement errors and reduced timeliness. In contrast, the dual-gated integrator architecture alternates between two integrators to complete integration and discharge, ensuring real-time and continuous processing of current signals and providing dead-time-free readout. This is especially critical for rapid response and high-accuracy dose measurements.

2. Attenuation Circuit

As shown in Fig. 4, the attenuation circuit follows the multiplexer circuit at the backend. The voltage amplitude range of the output from the front-end multiplexer circuit is between -10V and 10V. To reduce the power consumption of the circuit and match the signal processing range of the data acquisition circuit in the subsequent stage, a voltage attenuation circuit is designed to attenuate the signal within the -10V to 10V range to between -1V and 1V. The attenuation is implemented using the T-attenuation circuit, as shown in Fig. 8 [FIGURE:8].

Fig. 8. T-attenuation circuit.

The calculation method for the resistance of the circuit is given by Eq. (6), where $R_c$ is the circuit impedance matching resistance of 50Ω, and $N$ is the attenuation factor.

$$R_1 = R_c \frac{N - 1}{N + 1}$$
$$R_2 = R_c \frac{2N}{N^2 - 1}$$

From the above equation, the resistance in this circuit are calculated as $R_1=10 \text{ kΩ}$, $R_2=560 \text{ Ω}$. The voltage signal amplitude after passing through the attenuation circuit is ±1 V, which is then fed directly to the data acquisition circuit through a subsequent stage follower circuit.

B. DAQ Circuit Board

As shown in Fig. 9 [FIGURE:9], the DAQ circuit primarily consists of the front-end preprocessing unit (Pre-Processing Unit, PPU) and the data processing unit (Data Processing Unit, DPU).

Fig. 9. Schematic of DAQ circuit.

The PPU amplifies and filters the raw voltage signals output by the AFE, shaping them before they are sampled by the on-board 14-bit ADC and converted into digital signals. These digital signals are then forwarded to the DPU for further signal processing and computation. The DPU handles data flow algorithm processing, transmission, command reception and parsing, as well as clock control. An image of the DAQ circuit board is shown in Fig. 10 [FIGURE:10].

Fig. 10. Image of the DAQ circuit board.

1. PPU Unit

The PPU (Pre-Processing Unit) consists of four main components: a matching and protection circuit, a gain amplification circuit, an anti-aliasing filter, and an ADC sampling circuit. To minimize signal reflection and enhance measurement accuracy, terminal matching is used at the input for proper impedance matching. The filter shaping circuit is used to eliminate high-frequency noise. To simplify the circuit structure while achieving optimal filtering performance and serving as the driver circuit for the ADC, the design adopts a second-order low-pass anti-aliasing filter characterized by low noise, low distortion, and wide bandwidth.

2. DPU Unit

The hardware structure of the DPU unit consists mainly of a Field-Programmable Gate Array (FPGA) and its peripheral circuits, providing the sampling clock for the ADC and supplying clock and synchronization signals for the internal data processing modules of the FPGA. The DPU also includes multiple interfaces to control the AFE circuit. The data transmission interface includes an optical fiber transmission interface and a Universal Serial Bus (USB) interface. The host computer sends instructions to the FPGA via USB. After receiving the instructions, the FPGA controls operations such as ADC sampling and FIFO caching, and then transmits the acquired signals to the host computer through the USB transmission circuit.

III. SYSTEM FIRMWARE DESIGN

The system firmware design has two main parts: one controls the high-speed switches and signal reading of the gated integrator on the AFE board using a CPLD, while the other manages ADC sampling, data processing, packaging, uploading, and communication with the host computer.

A. AFE Circuit Firmware Design

Fig. 11 [FIGURE:11] shows the diagram of the gated integrator, where different capacitors can be selected based on the input.

Fig. 11. The diagram of the gated integrator.

Fig. 12 [FIGURE:12] illustrates the complete integration cycle, consisting of four stages: discharge, wait, integration, and hold.

Fig. 12. Complete Integration Cycle of the Gated Integrator.

1. Discharge: SH is set to high and SR to low, grounding the capacitors in the gated integrator and starting the discharge.
2. Wait: Set both SH and SR to high to prepare for integration, disconnecting SR to prevent charge flow to the ground. The wait time should be at least 10 ps for stabilization.
3. Integration: SH is set to low and SR to high, activating SH and charging the capacitor.
4. Hold: Set both SH and SR to high, deactivating SH and halting the integrator's operation.

The AFE firmware design involves the CPLD's logic control of the dual-gated integrator, multiplexer, and other components. The timing diagram is shown in Fig. 15 [FIGURE:15], where Clock is the system clock provided by an external crystal oscillator; TrigIn is the external trigger signal corresponding to the operating cycle. SHA and SHB are the integration switches for integrators A and B, respectively, while SRA and SRB are the discharge switches for integrators A and B, all of which are active low. Daqtrig is the acquisition trigger signal sent from the AFE circuit to the DAQ circuit, instructing the ADC when to sample data. OUTPUT refers to the output signals, where channel A corresponds to integrator A's output, and channel B to integrator B's output.

Fig. 15. The AFE circuit timing diagram.

B. DAQ Circuit Firmware Design

The DAQ circuit firmware design mainly includes logic control for FPGA data framing and packaging, AFE triggering, USB commands and data transmission.

1. AFE triggering, USB commands and Data transmission

The AFE trigger signal, TrigIn, defines the circuit's operation. The AFE operates based on the period of TrigIn, with integration duration and gain directly related to its period. The system diagram for AFE triggering, USB commands, and data transmission is shown in Fig. 13 [FIGURE:13].

Fig. 13. System Diagram for AFE Triggering, USB Commands, and Data Transmission.

The host computer sends commands and integration duration via USB to the FPGA in the DAQ circuit. The FPGA parses the commands, restores the waveform, and generates a correct TrigIn signal, which controls the AFE's operation time and cycle. Once the AFE is active, the output signal is sampled by the DAQ circuit, and the FPGA processes and packages the data, which is then uploaded to the host computer via USB. Fig. 14 [FIGURE:14] illustrates the complete process of a read-write operation state transition between the FPGA and USB. The fifo empty and fifo full signals shown in the figure represent the FIFO status signals of the USB chip.

Fig. 14. State Transition Diagram of FPGA and USB Communication.

The data reading process consists of three states: idle, reading, and continue reading or waiting.

1. Idle state: After reset, the system waits for the trigger condition in the IDLE state.
2. Reading state: If the read enable is active and the FIFO is not empty (Rd_en & !fifo_empty), the system enters the reading state, where the FPGA performs the read operation and increments the read counter. Otherwise, it returns to the IDLE state.
3. Continue reading or waiting state: After reading one data, the system checks if the read enable is active and the FIFO is not empty (Rd_en & !fifo_empty). If valid, it continues reading data; otherwise, it transitions to the IDLE state waiting for the trigger condition.

The data writing process consists of three states: idle, writing, and continue writing or waiting.

1. Idle state: After reset, the system waits for the trigger condition in the IDLE state.
2. Writing state: If the write enable is active and the FIFO is not full (Wr_en & !fifo_full), the system enters the writing state, where the FPGA performs the write operation and increments the write counter. Otherwise, it returns to the IDLE state.
3. Continue writing or waiting state: After writing one data, the system checks if the write enable is active and the FIFO is not full (Wr_en & !fifo_full). If valid, it continues writing data; otherwise, it transitions to the IDLE state waiting for the trigger condition.

2. Data framing and packaging

After the ADC samples and quantizes the analog voltage signal, it outputs a 14-bit parallel data stream. The signal is framed in a specific data format for easy extraction and analysis. As shown in Fig. 16 [FIGURE:16], each data set consists of 33 sampling points. The framed data is stored in an asynchronous FIFO (First In, First Out) buffer, from which the data packaging module packages and transmits the data. The header (55AA) and footer (5AA5) identify the packet, with the second bit indicating the channel (integrator A or B). Bits 3 to 6 are reserved for future use, while the remaining bits contain the 33 sampled data points.

Fig. 16. Data format.

3. Baseline restoration

The ADC sampled data is temporarily stored in the FIFO. When the data read condition is met, the FIFO read enable is triggered to retrieve the data, which serves as the basis for subsequent pulse baseline calculations. Since baseline drift may occur due to the detector and conditioning circuitry, baseline calibration is required. The FPGA controls the ADC to sample N points and compute the average, yielding the current baseline value, $B_{AVG}$, as shown in Eq. (7):

$$B_{AVG} = \frac{1}{N} \sum_{i=1}^{N} V_i$$

Where $V_i$ is the amplitude of the $i$th sampled waveform point.

After baseline calculation, the charge is determined by summing the data of M sampled points, as shown in Eq. (8):

$$Q = K \sum_{i=1}^{M} (V_i - B_{AVG}) \cdot \Delta t$$

Where $K$ is the conversion gain of the conditioning circuit, and $\Delta t$ is the sampling time for each sample.

4. Real-time host computer software design

The host computer software interface, shown in Fig. 17 [FIGURE:17], allows for selecting the data format, setting the integration duration, and configuring the FPGA. The right side displays a plotting area where data is processed by two threads: one stores the data in a ".dat" file, while the other performs real-time analysis and plotting. During event analysis, 33 sampled points can reconstruct the complete waveform. However, since this work focuses on amplitude, the points from the 20th to the 30th, where the amplitude is stable, are selected for calculation. To minimize errors from baseline drift, the first five points of the 33 are used as baseline pre-samples. The accurate peak-to-peak amplitude is obtained by subtracting the baseline from the stable amplitude value. The AFE system uses a dual-gated integrator architecture, and to reduce errors introduced by the integrators, standard charge values are used in the host software to correct both integrators A and B.

Fig. 17. Host computer software.

IV. PERFORMANCE TEST

A. Electronics Performance Test

1. Calibration of the Integration Capacitance

In laboratory tests, a 100 pF on-chip integrating capacitor is used for integration. Fig. 18 [FIGURE:18] shows the linearity characteristics between the integrator's measured and theoretical charge outputs at different integration times (20 µs, 50 µs, 100 µs, 500 µs). The red circles represent the theoretical charge output, while the orange (500 µs), blue (100 µs), green (50 µs), and purple (20 µs) circles represent the measured charge output for various conditions. Significant deviations are observed, primarily due to the discrepancy between the actual and nominal values of the integrator capacitor. To reduce this error, the capacitance was calibrated, and the results were compensated using the corrected capacitance. After calibration, as shown in Fig. 19 [FIGURE:19], the error between the measured and theoretical charge outputs is significantly reduced, with measurements closely matching the theoretical values. The maximum nonlinear error after correction is 0.55% (the linear correlation coefficient R² = 0.99996). The T-shaped symbols within the hollow circles in Fig. 18 and Fig. 19 represent the standard deviation error bars, which are calculated according to Eq. (9). Each data point in this test was measured five times, with a total of 400 sets of measurements.

$$\sigma = \sqrt{\frac{1}{N-1} \sum_{i=1}^{N} (x_i - \bar{x})^2}$$

Where $x_i$ is a data point, $\bar{x}$ is the mean value, and $N$ is the sample size.

Fig. 18. AFE output charge error vs. theoretical charge at different integration durations.

Fig. 19. After Calibration AFE output charge error vs. theoretical charge at different integration durations.

2. Nonlinear Error Test

With the integrator capacitor fixed at 100 pF, the measurable current dynamic range varies with different integration times. Five integration times are selected as distinct ranges, and fitting is performed using Origin to calculate the nonlinear error over the entire range. The results are shown in Table 2 [TABLE:2]. When the integration time is 1 s and the capacitor is 0.5 pF, the laboratory-measured minimum current range is -1 pA to 1 pA.

TABLE 2. Integral nonlinearity error at different integration durations.

Integration Time (Capacitance) Current Measurement Range NonLinear Error (Measurement Dead Zone) 5 µs (100 pF) -190 µA to 200 µA (-180 nA to 180 nA) 0.67% (R²=0.99992) 20 µs (100 pF) -50 µA to 50 µA (-30 nA to 30 nA) 0.35% (R²=0.99998) 50 µs (100 pF) -20 µA to 20 µA (-12 nA to 12 nA) 0.24% (R²=1.00000) 100 µs (100 pF) -10 µA to 10 µA (-8 nA to 8 nA) 0.42% (R²=1.00000) 500 µs (100 pF) -2 µA to 2 µA (-1 nA to 1 nA) 0.52% (R²=0.99996) 1 s (0.5 pF) -4 pA to 4 pA (-1 pA to 1 pA) 0.24% (R²=0.99993)

Fig. 20 [FIGURE:20] shows the linear fit curve for the entire measurement range. The nonlinear error of the range from -190 µA to 200 µA is 0.67% and the coefficient of determination is R²=0.99992. The tests demonstrate that the system offers high accuracy, a wide dynamic range, good linearity, and excellent performance in ultra-low current measurements.

Fig. 20. Nonlinear error and coefficient of determination in the full range.

B. Beam Experiment

To verify the system's real-time monitoring capability at high dose rates, in April 2024, after the whole electronics system was completed, beam tests were performed with an ionization chamber detector in the TR4 terminal of the Heavy Ion Research Facility in Lanzhou (HIRFL). The TR4 terminal uses heavy ions with varying dose rates for fundamental research on heavy ion cancer therapy and clinical trials for treating superficial tumors in humans. The beam experiment layout is shown in Fig. 21 [FIGURE:21]. The carbon ion beam is extracted into the atmosphere, passing through a dose ionization chamber detector, which converts the ion signal into a current. This current is then input into the real-time dosimetry monitoring system. The host computer, located in the control room, remotely controls data acquisition via cables.

Fig. 21. Beam test scheme diagram.

The field image of the test, shown in Fig. 22 [FIGURE:22], includes the ionization chamber detector (a), which transmits the current signal to the AFE (b) for voltage conversion. The DAQ (c) samples and processes the signal, with results displayed on the host computer. Prior to the experiment, all integrator capacitance values were calibrated in the laboratory to ensure accurate results. In conventional and high dose rate radiotherapy, the dose rate is typically below 20 Gy/min. Monitoring at higher dose rates imposes stricter demands on the system's dynamic range, response rate, stability, and accuracy. To evaluate the system's real-time monitoring performance at higher dose rates, this experiment set the beam dose range between 65 Gy/min and 120 Gy/min. The terminal dose is updated every second, with the AFE circuit using a 10 pF capacitor and an integration time of 16 µs, corresponding to 62,500 events per second.

Fig. 22. Beam test field diagram.

After analyzing the sampled current signals, a linear fit curve of ionization chamber output current versus dose variation is shown in Fig. 23 [FIGURE:23]. Each data point represents the current at different beam dose levels, with the coefficient of determination being R²=0.9998. The results show that the system can stably operate at dose rates up to 120 Gy/min, meeting the real-time monitoring requirements for both conventional and high dose rate radiotherapy, and demonstrating potential for application in ultra-high dose rate radiotherapy (FLASH-RT).

Fig. 23. Linear fit of ionization chamber output current vs dose rate.

V. DISCUSSION

In 2010, Furukawa and Torikoshi M from the National Institute of Radiological Sciences (NIRS), Japan, measured dosimetry for HIMAC with a range of 1 nA to 1000 nA, a nonlinear error of less than 1%, and a dose rate of approximately 1 Gy/min. In 2017, Binqing Zhao from the Shanghai Institute of Applied Physics, Chinese Academy of Sciences, developed a proton therapy beam delivery system with a dosimetry range of -400 nA to -60 nA, a dose rate of about 2 Gy/min, and a maximum linear error of ±0.04 nA. In 2020, Eric S. Diffenderfer's team at the University of Pennsylvania designed a proton FLASH-RT system with a dose rate of 60-100 Gy/s and a maximum beam current of 300 nA, showing a linear relationship between proton current and dose rate (R² = 0.9952). In 2024, M. Yagi and colleagues developed dosimetry electronics for HIMAC's UHDR carbon ion beam with a range of -0.5 µA to -50 µA, dose rates up to 102.54-115.38 Gy/s, and a linear relationship between ion chamber current and electronics output frequency within ±1%.

Compared to existing dosimetry electronics systems, this system offers a measurement range of ±1 pA to ±200 µA, capable of reading both positive and negative signals, with a nonlinear error of < 0.62% (R² = 0.99992). It meets the ionization chamber current monitoring needs of most conventional and FLASH-RT dose detectors. Owing to the fact that domestic FLASH radiotherapy terminals are still in development, this system has not yet been validated with FLASH beams. Nonetheless, its wide dynamic range, high linearity, and dead-time-free features demonstrate significant potential for future FLASH-RT research and clinical applications. In future work, we will further optimize the experimental design and systematically explore and establish a feasible and reasonable error evaluation method, determining and including error bars in similar measurements.

VI. CONCLUSION

This work demonstrates an innovative real-time dosimetry monitoring system for heavy ion radiotherapy, validated experimentally on the TR4 terminal. The system detects bipolar currents within a range of -190 µA to 210 µA, maintains a nonlinear error below 0.67%, and offers a single-event processing time as fast as 5 µs. The system achieved high-accuracy real-time monitoring within a dose rate range of 65-120 Gy/min in beam experiments. Compared to existing radiotherapy dosimetry systems, it eliminates signal processing dead time in the front-end circuit, ensuring continuous and accurate dose measurements. The system's current measurement range spans eight orders of magnitude (±1 pA to ±190 µA), greatly enhancing its versatility across different applications. This system is optimized for high-precision monitoring of ionization chamber output currents and is compatible with various radiotherapy modes. It is suitable for real-time dose measurement in heavy ion radiotherapy and can be extended to electron, proton, and other high-energy particle radiotherapies, demonstrating broad application potential. To meet the growing demand for higher dose rates and support cutting-edge applications like FLASH-RT, we are developing a new generation of ultra-fast front-end processing circuits and data acquisition systems. This system will offer a sampling rate up to 250 MHz, data transmission speeds over 10 GHz, and a wider input dynamic range, enhancing real-time monitoring capabilities in high dose rate environments. These improvements will not only expand the system's applicability in high dose rate radiotherapy but also provide a more reliable real-time dosimetry solution for accurate radiotherapy.

REFERENCES

[1] R. He, X. Y. Niu, Y. Wang, et al., Advances in nuclear detection and readout techniques, Nucl. Sci. Technol. 34, 281-358 (2023). doi:10.1007/s41365-023-01359-0
[2] K. Parodi, Heavy ion radiography and tomography. Phys. Med. 30, 539–543 (2014). doi:10.1016/j.ejmp.2014.02.004
[3] J.W. Yan, Design of In-Beam PET Readout Electronics for Heavy Ion Cancer Therapy Devices, PhD Thesis, University of Chinese Academy of Sciences, 2020. (in Chinese)
[4] G. Kraft, Tumor therapy with heavy charged particles, Prog. Part. Nucl. Phys. 45, S473-S544 (2000). doi: 10.1016/S0146-6410(00)00112-5
[5] J. Liu, G. Zhou, H. Pei, The clinical prospect of FLASH radiotherapy, Radiat. Med. Prot. 4(4), 190-196 (2023). doi: 10.1016/j.radmp.2023.10.005
[6] E. Schüler, M. Acharya, P. Montay-Gruel, et al., Ultra-high dose rate electron beams and the FLASH effect: From preclinical evidence to a new radiotherapy paradigm, Med. Phys. 49, 2082-2095 (2022). doi: 10.1002/mp.15442
[7] J. C. L. Chow, H. E. Ruda, Flash Radiotherapy: Innovative Cancer Treatment, Encyclopedia 3, 808-823 (2023). doi: 10.3390/encyclopedia3030058
[8] J. C. L. Chow, H. E. Ruda, Mechanisms of Action in FLASH Radiotherapy: A Comprehensive Review of Physicochemical and Biological Processes on Cancerous and Normal Cells, Cells 13, 835 (2024). doi: 10.3390/cells13100835
[9] G. Rosini, E. Ciarrocchi, B. D'Orsi, Mechanisms of the FLASH effect: current insights and advances, Front. Cell Dev. Biol. 13, 1575678 (2025). doi: 10.3389/fcell.2025.1575678
[10] L. Lin, N. Kane, N. Kobayashi, et al., High-dose per Fraction Radiotherapy Induces Both Antitumor Immunity and Immunosuppressive Responses in Prostate Tumors, Clin. Cancer Res. 27, 1505-1515 (2021). doi: 10.1158/1078-0432.CCR-20-2293
[11] S. Hornsey, D. K. Bewley, Hypoxia in mouse intestine induced by electron irradiation at high dose-rates, Int. J. Radiat. Biol. 19, 479-483 (1971). doi: 10.1080/09553007114550611
[12] V. Favaudon, L. Caplier, V. Monceau, et al., Ultrahigh dose-rate FLASH irradiation increases the differential response between normal and tumor tissue in mice, Science Translational Medicine 6, 245ra93 (2014). doi: 10.1126/scitranslmed.3008973
[13] A. Patriarca, C. Fouillade, M. Auger, et al., Experimental Set-up for FLASH Proton Irradiation of Small Animals Using a Clinical System, Int. J. Radiat. Oncol. Biol. Phys. 102, 619-626 (2018). doi: 10.1016/j.ijrobp.2018.06.403
[14] Kim MM, Verginadis II, Goia D, et al., Comparison of FLASH Proton Entrance and the Spread-Out Bragg Peak Dose Regions in the Sparing of Mouse Intestinal Crypts and in a Pancreatic Tumor Model, Cancers (Basel). 13, 4244 (2021). doi:10.3390/cancers13164244
[15] T. Evans, J. Cooley, M. Wagner, et al., Demonstration of the FLASH Effect Within the Spread-out Bragg Peak After Abdominal Irradiation of Mice, Int. J. Part. Ther. 8, 68-75 (2022). doi: 10.14338/IJPT-20-00095
[16] A. Mascia, S. McCauley, J. Speth, et al., Impact of Multiple Beams on the FLASH Effect in Soft Tissue and Skin in Mice, Int. J. Radiat. Oncol. Biol. Phys. 118, 253-261 (2023). doi: 10.1016/j.ijrobp.2023.07.024
[17] I. I. Verginadis, A. Velalopoulou, M. M. Kim, et al., FLASH proton reirradiation, with or without hypofractionation, reduces chronic toxicity in the normal murine intestine, skin, and bone, Radiother. Oncol. 205, 110744 (2025). doi: 10.1016/j.radonc.2025.110744
[18] V. Patera, A. Sarti, Recent Advances in Detector Technologies for Particle Therapy Beam Monitoring and Dosimetry, IEEE Trans. Radiat. Plasma Med. Sci. 4, 133-146 (2020). doi: 10.1109/TRPMS.2019.2951848
[19] P. Andreo, M. Saiful Huq, M. Westermark, et al., Protocols for the dosimetry of high-energy photon and electron beams: A comparison of the IAEA TRS-398 and previous international Codes of Practice, Phys. Med. Biol. 47, 3033-3053 (2002). doi: 10.1088/0031-9155/47/17/301
[20] P. R. Almond, P. J. Biggs, B. M. Coursey, et al., AAPM's TG-51 protocol for clinical reference dosimetry of high-energy photon and electron beams, Med. Phys. 26, 1847-1870 (1999). doi: 10.1118/1.598691
[21] S. Giordanengo, M. Donetti, M. A. Garella, et al., Design and characterization of the beam monitor detectors of the Italian National Center of Oncological Hadron-therapy (CNAO), Nucl. Instrum. Methods Phys. Res. A 698, 202-207 (2013). doi: 10.1016/j.nima.2012.10.004
[22] S.X. Lin, T. Boehringer, A. Coray, et al., More than 10 years experience of beam monitoring with the Gantry 1 spot scanning proton therapy facility at PSI, Med. Phys. 36, 5331-5340 (2009). doi: 10.1118/1.3244034
[23] C. P. Karger, G. H. Hartmann, O. Jäkel, et al., Quality management of medical physics issues at the German heavy ion therapy project, Med. Phys. 27, 725-736 (2000). doi: 10.1118/1.598935
[24] B. Arjomandy, N. Sahoo, X. Ding, et al., Use of a two-dimensional ionization chamber array for proton therapy beam quality assurance, Med. Phys. 35, 3889-3894 (2008). doi: 10.1118/1.2963990
[25] L. Lin, M. Kang, T. D. Solberg, et al., Use of a novel two-dimensional ionization chamber array for pencil beam scanning proton therapy beam quality assurance, J. Appl. Clin. Med. Phys. 16, 270-276 (2015). doi: 10.1120/jacmp.v16i3.5323
[26] S. Siddique, H. E. Ruda, J. C. L. Chow, FLASH Radiotherapy and the Use of Radiation Dosimeters, Cancers 15, 3883 (2023). doi: 10.3390/cancers15153883
[27] K. Polaczek-Grelik, A. Kawa-Iwanicka, L. Michalecki, Dosimetric accuracy of a cross-calibration coefficient for plane-parallel ionization chamber obtained in low-energy electron beams using various cylindrical dosimeters, Pol. J. Med. Phys. Eng. 27, 303-313 (2021). doi: 10.2478/pjmpe-2021-0036
[28] C. P. Karger, O. Jäkel, H. Palmans, et al., Dosimetry for ion beam radiotherapy, Phys. Med. Biol. 55, R193 (2010). doi: 10.1088/0031-9155/55/21/R01
[29] Q. S. She, Y. Qian, J. Kong, et al., Design of fast adaptive readout system for wire scanners, Nucl. Sci. Tech. 29, 15 (2018). doi: 10.1007/s41365-017-0343-3
[30] T. Furukawa, T. Inaniwa, S. Sato, et al., Performance of the NIRS fast scanning system for heavy-ion radiotherapy, Med. Phys. 37, 5672-5682 (2010). doi: 10.1118/1.3501313
[31] S. Amerio, A. Boriano, F. Bourhaleb, et al., Dosimetric characterization of a large area pixel-segmented ionization chamber, Med. Phys. 31, 414-420 (2004). doi: 10.1118/1.1639992
[32] D. Nichiporov, K. Solberg, W. Hsi, M. Wolanski, et al., Multichannel detectors for profile measurements in clinical proton fields, Med. Phys. 34, 2683-2690 (2007). doi: 10.1118/1.2746513
[33] E. S. Diffenderfer, I. I. Verginadis, M. M. Kim, et al., Design, Implementation, and in Vivo Validation of a Novel Proton FLASH Radiation Therapy System, Int. J. Radiat. Oncol. Biol. Phys. 106, 440-448 (2020). doi: 10.1016/j.ijrobp.2019.12.007
[34] M. Yagi, S. Shimizu, N. Hamatani, et al., Development and characterization of a dedicated dose monitor for ultrahigh-dose-rate scanned carbon-ion beams, Sci. Rep. 14, 11574 (2024). doi: 10.1038/s41598-024-62148-2
[35] G. C. Bonazzola, G. Mazza, A VLSI circuit for charge measurement of a strip ionization chamber, Nucl. Instrum. Methods Phys. Res. A 409, 336-338 (1998). doi: 10.1016/S0168-9002(97)01293-X
[36] F. Fausti, G. Mazza, S. Giordanengo, O. H. Ali, et al., Single Event Upset tests and failure rate estimation for a front-end ASIC adopted in high-flux-particle therapy applications, Nucl. Instrum. Methods Phys. Res. A 918, 54-59 (2019). doi: 10.1016/j.nima.2018.11.106
[37] Q.S. She, Design of fast adaptive readout system for wire scanners, PhD Thesis, University of Chinese Academy of Sciences, 2019. (in Chinese)
[38] T. Wang, Application of fast multi-channel readout system for beam profile measurement, PhD Thesis, University of Chinese Academy of Sciences, 2024. (in Chinese)
[39] B.Q. Zhao, Study on the electronics of ionization chamber for proton therapy beam shaping system, PhD Thesis, Shanghai Institute of Applied Physics, Chinese Academy of Sciences, 2017. (in Chinese)
[40] G. C. Bonazzola, R. Cirio, M. Donetti, et al., Performances of a VLSI wide dynamic range current-to-frequency converter for strip ionization chambers, Nucl. Instrum. Methods Phys. Res. A 405, 111-120 (1998). doi: 10.1016/S0168-9002(97)01209-6
[41] M. Torikoshi, K. Noda, E. Takada, et al., Beam monitor system for high-energy beam transportation at HIMAC, Nucl. Instrum. Methods Phys. Res. A 435, 326-338 (1999). doi: 10.1016/S0168-9002(99)00569-0